component
LDTD113ZLT1G
Public Made by Adomby adom
LRC Digital Transistors, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LDTD113ZLT1G
LRC · Digital Transistors · SOT-23
LDTD113ZLT1G from LRC, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BASE | input | Base input of the NPN transistor, connected through the built-in bias resistor R1 (1 kΩ) so no external input resistor is needed; input voltage limit is −5 V to +10 V. |
| 2 | EMITTER | passive | Emitter of the NPN transistor, the reference terminal for the base bias resistor R2 (10 kΩ) network. |
| 3 | COLLECTOR | passive | Collector of the NPN transistor, rated for a supply voltage of 50 V and an output current of 500 mA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SOT-23 |
| Category | Transistors/Thyristors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage (off) | VI(off) | 0.3 | V | VCC=5V, IO=100µA | 1 | ||
| Input voltage (on) | VI(on) | 1.5 | V | VO=0.3V, IO=20mA | 1 | ||
| Output voltage (on) | VO(on) | 0.1 | 0.3 | V | IO/II=50mA/2.5mA | 1 | |
| Input current | II | 7.2 | mA | VI=5V | 1 | ||
| Output current (off) | IO(off) | 0.5 | µA | VCC=50V, VI=0V | 1 | ||
| Input resistance | R1 | 0.7 | 1 | 1.3 | kΩ | 1 | |
| DC current gain | GI | 82 | VO=5V, IO=50mA | 1 | |||
| Resistance ratio | R2/R1 | 8 | 10 | 12 | 1 | ||
| Transition frequency | fT | 200 | MHz | VCE=10V, IE=−50mA, f=100MHz | 1 | ||
| Supply voltage | VCC | 50 | V | Ta=25°C | 1 | ||
| Input voltage | VIN | -5 | 10 | V | Ta=25°C | 1 | |
| Output current | IC | 500 | mA | Ta=25°C | 1 | ||
| Power dissipation | PD | 200 | mW | Ta=25°C | 1 | ||
| Junction temperature | Tj | 150 | °C | Ta=25°C | 1 | ||
| Storage temperature | Tstg | -55 | 150 | °C | Ta=25°C | 1 |
CAD (KiCad official)
- Symbol:
LDTD113ZLT1G - Footprint:
Package_TO_SOT_SMD:SOT-23 - 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files:
ldtd113zlt1g-etched.step/ldtd113zlt1g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ldtd113zlt1g.step/ldtd113zlt1g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: LRC datasheet (3 pp, sha256
2d22ed0d0a37896b, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LDTD113ZLT1G
**LRC** · Digital Transistors · SOT-23
LDTD113ZLT1G from LRC, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BASE | input | Base input of the NPN transistor, connected through the built-in bias resistor R1 (1 kΩ) so no external input resistor is needed; input voltage limit is −5 V to +10 V. |
| 2 | EMITTER | passive | Emitter of the NPN transistor, the reference terminal for the base bias resistor R2 (10 kΩ) network. |
| 3 | COLLECTOR | passive | Collector of the NPN transistor, rated for a supply voltage of 50 V and an output current of 500 mA. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SOT-23 |
| Category | Transistors/Thyristors |
| Pins | 3 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage (off) | VI(off) | | | 0.3 | V | VCC=5V, IO=100µA | 1 |
| Input voltage (on) | VI(on) | 1.5 | | | V | VO=0.3V, IO=20mA | 1 |
| Output voltage (on) | VO(on) | | 0.1 | 0.3 | V | IO/II=50mA/2.5mA | 1 |
| Input current | II | | | 7.2 | mA | VI=5V | 1 |
| Output current (off) | IO(off) | | | 0.5 | µA | VCC=50V, VI=0V | 1 |
| Input resistance | R1 | 0.7 | 1 | 1.3 | kΩ | | 1 |
| DC current gain | GI | 82 | | | | VO=5V, IO=50mA | 1 |
| Resistance ratio | R2/R1 | 8 | 10 | 12 | | | 1 |
| Transition frequency | fT | | 200 | | MHz | VCE=10V, IE=−50mA, f=100MHz | 1 |
| Supply voltage | VCC | | | 50 | V | Ta=25°C | 1 |
| Input voltage | VIN | -5 | | 10 | V | Ta=25°C | 1 |
| Output current | IC | | | 500 | mA | Ta=25°C | 1 |
| Power dissipation | PD | | | 200 | mW | Ta=25°C | 1 |
| Junction temperature | Tj | | | 150 | °C | Ta=25°C | 1 |
| Storage temperature | Tstg | -55 | | 150 | °C | Ta=25°C | 1 |
## CAD (KiCad official)
- Symbol: `LDTD113ZLT1G`
- Footprint: `Package_TO_SOT_SMD:SOT-23`
- 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files: `ldtd113zlt1g-etched.step` / `ldtd113zlt1g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ldtd113zlt1g.step` / `ldtd113zlt1g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [LRC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884483239497728) (3 pp, sha256 `2d22ed0d0a37896b`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ldtd113zlt1g-datasheet.pdf)