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LDC1001EPWRQ1

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Texas Instruments ADC/DAC - Specialized, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LDC1001EPWRQ1

Texas Instruments · ADC/DAC - Specialized · TSSOP-16

LDC1001EPWRQ1 from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SCLK input SPI clock input used to clock data out of and into the chip.
2 CSB input SPI chip select (active low); allows multiple devices on the same SPI bus and selects which device is communicated with.
3 SDI input SPI slave data in (Master Out Slave In), connected to the master's MOSI output.
4 VIO power_in Digital IO supply, recommended 1.8 V to 5.25 V.
5 SDO tri_state SPI slave data out (Master In Slave Out); high-Z when CSB is high.
6 DGND power_in Digital ground.
7 CFB passive LDC filter capacitor pin.
8 CFA passive LDC filter capacitor pin.
9 INA passive External LC tank connection; connect to an external LC tank.
10 INB passive External LC tank connection; connect to an external LC tank.
11 GND power_in Analog ground.
12 VDD power_in Analog supply, recommended 4.75 V to 5.25 V.
13 CLDO passive LDO bypass capacitor pin; connect a 56-nF capacitor from this pin to GND.
14 TBCLK input External time-base clock input for the frequency counter.
15 NC unconnected Not connected internally; this pin should be left floating.
16 INTB output Configurable interrupt output; can function as threshold detect, wake-up, or DRDYB via the INT pin mode register.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category ADC/DAC/Data Conversion
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analog supply voltage VDD 4.75 5 5.25 V 5
IO supply voltage VIO 1.8 3.3 5.25 V VIO ≤ VDD 5
Supply current IDD 1.7 2.3 mA Does not include the LC tank current 5
Logic 0 output voltage VOL 0.3 V I(SINK) = 400 µA 5
Digital IO leakage current IlkgIO -500 500 nA 5
External clock frequency 8 MHz 5
Analog supply voltage (recommended) VDD 4.75 5.25 V VDD, GND 4
IO supply voltage (recommended) VIO 1.8 5.25 V VIO, GND 4
Operating temperature TA -40 150 °C 4
Serial clock frequency fSCLK 4 MHz See Figure 1 6
SDI setup time tsu 10 ns See Figure 1 6
SDI hold time th 10 ns See Figure 1 6
SDO driven-to-tristate time tODZ 20 ns Measured at 10% / 90% point, See Figure 2 6
SDO tristate-to-driven time tOZD 20 ns Measured at 10% / 90% point, See Figure 2 6
SDO output delay time td(OUTPUT) 20 ns See Figure 2 6
CSB setup time tsu(CS) 20 ns 6
CSB hold time th(CS) 20 ns 6
Inter-access gap tIAG 100 ns See Figure 16 6
Analog supply voltage VDD, GND VDD 5.5 V 4
IO supply voltage VIO, GND VIO 5.5 V 4
Voltage on any pin (min) -0.3 V On any pin 4
Voltage on any digital pin (min) -0.3 V On any digital pin 4
Input current INA and INB 8 mA 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -65 150 °C 4
ESD HBM V(ESD) -2000 2000 V Human body model, per AEC Q100-002 4
ESD CDM V(ESD) -1000 1000 V Charged device model, per AEC Q100-011 4
Junction-to-ambient thermal resistance RθJA 106.3 °C/W PW (TSSOP) 16 pins 4
Junction-to-case (top) thermal resistance RθJC(top) 40.8 °C/W PW (TSSOP) 16 pins 4
Junction-to-board thermal resistance RθJB 51.3 °C/W PW (TSSOP) 16 pins 4
Junction-to-top characterization parameter ψJT 3.6 °C/W PW (TSSOP) 16 pins 4
Junction-to-board characterization parameter ψJB 50.8 °C/W PW (TSSOP) 16 pins 4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper For this example, the selected capacitor value is 20 pF. The following waveforms were taken on the CFB pin with a 14-mm, 2-layer PCB coil (23 turns, 4-mil trace width, 4-mil spacing between trace, 1-o 30

CAD (KiCad official)

  • Symbol: LDC1001EPWRQ1
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: ldc1001epwrq1-etched.step / ldc1001epwrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ldc1001epwrq1.step / ldc1001epwrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (42 pp, sha256 9e344189c5ca3b90, retrieved 2026-10-24, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF