# LD7750RGR

**Leadtrend Tech** · AC-DC Controllers And Regulators · SOP-7

LD7750RGR from Leadtrend Tech, in a SOP-7. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OTP | input | Pulling this pin below 0.95V shuts the controller down into latch mode until AC power recycles; a NTC to ground provides over-temperature protection, and leaving it floating disables the latch protection. |
| 2 | COMP | input | Voltage feedback pin that receives the photo-coupler feedback to close the regulation loop, and pulling it below 1.8V turns the controller off. |
| 3 | CS | input | Current sense pin for sensing the MOSFET current, with a maximum input voltage (Vcs_off) of 0.80 to 0.90V (0.85V typical) and 250ns leading-edge blanking. |
| 4 | GND | power_in | Ground reference pin for the controller. |
| 5 | OUT | output | Gate drive output that drives the external power MOSFET, with a driving capability of 500mA. |
| 6 | VCC | power_in | Supply voltage pin, with UVLO turn-on at 15 to 17V (16V typical) and turn-off at 9 to 11V (10V typical), and Vcc OVP at 25 to 27V (26V typical). |
| 8 | HV | power_in | High-voltage startup pin connected to the positive terminal of the bulk capacitor (500V rating), which is turned off once Vcc reaches UVLO(on) to reduce startup power loss. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Leadtrend Tech |
| Package | SOP-7 |
| Category | Power Management (PMIC) |
| Pins | 7 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (VCC pin) | VCC | -0.3 |  | 30 | V |  | 4 |
| High-Voltage Pin (HV) | HV | -0.3 |  | 500 | V |  | 4 |
| COMP, OTP, CS pins |  | -0.3 |  | 7 | V |  | 4 |
| OUT pin | OUT | -0.3 |  |  | V | Upper limit printed as Vcc+0.3 | 4 |
| Gate Output Current |  |  |  | 500 | mA |  | 4 |
| Maximum Junction Temperature |  |  |  | 150 | °C |  | 4 |
| Operating Ambient Temperature |  | -20 |  | 85 | °C |  | 4 |
| Operating Junction Temperature |  | -40 |  | 125 | °C |  | 4 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 4 |
| Package Thermal Resistance (SOP-7/SOP-8) |  |  |  | 160 | °C/W |  | 4 |
| Power Dissipation (SOP-7/SOP-8) |  |  |  | 400 | mW | Ambient Temperature = 85°C | 4 |
| Lead temperature (soldering) |  |  |  | 260 | °C | 10 sec soldering | 4 |
| ESD Human Body Model (except HV pin) |  |  |  | 2.5 | KV |  | 4 |
| ESD Machine Model |  |  |  | 250 | V |  | 4 |
| High-Voltage Current Source |  | 0.5 | 1 | 1.5 | mA | VCC< UVLO(on), HV=500V | 5 |
| Startup Current |  | 200 | 320 | 400 | μA |  | 5 |
| UVLO (off) |  | 9 | 10 | 11 | V |  | 5 |
| UVLO (on) |  | 15 | 16 | 17 | V |  | 5 |
| OVP Level |  | 25 | 26 | 27 | V |  | 5 |
| Short Circuit Current |  | 0.2 | 0.26 | 0.32 | mA | VCOMP=0V | 5 |
| Open Loop Voltage |  | 5.5 |  | 6 | V | COMP pin open | 5 |
| Maximum Input Voltage (current sense off threshold) | Vcs_off | 0.8 | 0.85 | 0.9 | V |  | 5 |
| Oscillator Frequency |  | 61 | 65 | 69 | KHz |  | 6 |
| Trembling Frequency (frequency swapping range) |  | -4 |  | 4 | kHz |  | 6 |
| Temp. Stability |  |  | 5 |  | % | -20°C~85°C | 6 |
| Voltage Stability |  |  | 1 |  | % | VCC=11V-25V | 6 |
| OTP Pin Source Current |  | 92 | 100 | 108 | μA |  | 6 |
| OTP Turn-On Trip Level |  | 1 | 1.05 | 1.1 | V |  | 6 |
| OTP Turn-Off Trip Level |  | 0.9 | 0.95 | 1 | V |  | 6 |
| OLP Trip Level |  | 4.8 | 5 | 5.2 | V |  | 6 |
| Operating Current (with 1nF load on OUT pin) |  |  | 1.2 |  | mA | VCOMP=0V | 5 |
| Operating Current (with 1nF load on OUT pin) |  |  | 2.3 |  | mA | VCOMP=3V | 5 |
| Operating Current (with 1nF load on OUT pin) |  |  | 0.61 |  | mA | OLP tripped | 5 |
| Operating Current (with 1nF load on OUT pin) |  |  | 0.7 |  | mA | OVP tripped, VCC=OVP | 5 |
| Off-State Leakage Current |  |  | 35 |  | μA | VCC> UVLO(off), HV=500V | 5 |
| Green Mode Threshold |  |  | 2.75 |  | V | VCOMP | 5 |
| Zero Duty |  |  | 1.8 |  | V |  | 5 |
| Leading Edge Blanking Time |  |  | 250 |  | ns |  | 5 |
| Input impedance (CS pin) |  |  | 1 |  | MΩ |  | 5 |
| Delay to Output |  |  | 100 |  | ns |  | 5 |
| Green Mode Frequency |  |  | 20 |  | KHz |  | 6 |
| Output Low Level |  |  | 1 |  | V | VCC=15V, Io=20mA | 6 |
| Output High Level |  |  | 9 |  | V | VCC=15V, Io=20mA | 6 |
| Rising Time |  | 100 |  | 160 | ns | Load Capacitance=1000pF | 6 |
| Falling Time |  | 30 |  | 60 | ns | Load Capacitance=1000pF | 6 |
| OTP Pin De-latch VCC Level (PDR) |  |  | 8 |  | V |  | 6 |
| OLP Delay Time |  |  | 64 |  | ms |  | 6 |
| Soft Start Duration |  |  | 2 |  | ms |  | 6 |
| On Chip OTP Level |  |  | 140 |  | °C |  | 6 |
| On Chip OTP Hysteresis |  |  | 30 |  | °C |  | 6 |

## CAD (KiCad official)

- Symbol: `LD7750RGR`
- Footprint: `Package_SO:SOIC-8-N7_3.9x4.9mm_P1.27mm`
- 3D model: SOP-7 (KiCad packages3D, STEP)
- 3D model files: `ld7750rgr-etched.step` / `ld7750rgr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ld7750rgr.step` / `ld7750rgr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Leadtrend Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588903247344521216) (19 pp, sha256 `e33104d0046eba12`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ld7750rgr-datasheet.pdf)