# LD7750EGR

**Leadtrend Tech** · AC-DC Controllers And Regulators · SOP-7

LD7750EGR from Leadtrend Tech, in a SOP-7. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OTP | input | Pulling this pin below 0.95V shuts down the controller; an NTC from this pin to ground provides over-temperature protection, and leaving it floating or adding a 100kΩ resistor disables the latch protection. |
| 2 | COMP | input | Voltage feedback pin that receives the photo-coupler signal to close the control loop for regulation; pulling it below 1.8V turns the controller off. |
| 3 | CS | input | Current sense pin for sensing the MOSFET current, with a maximum input voltage threshold of 0.85V typical (0.80V to 0.90V). |
| 4 | GND | power_in | Ground reference for the controller. |
| 5 | OUT | output | Gate drive output that drives the external power MOSFET, with 500mA driving capability. |
| 6 | VCC | power_in | Supply voltage pin with UVLO thresholds of 16V (on) and 10V (off) and an absolute maximum rating of 30V. |
| 8 | HV | power_in | High-voltage pin connected to the positive terminal of the bulk capacitor to supply startup current, rated 500V, and turned off once VCC reaches UVLO(on). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Leadtrend Tech |
| Package | SOP-7 |
| Category | Power Management (PMIC) |
| Pins | 7 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage VCC | VCC | -0.3 |  | 30 | V |  | 4 |
| High-Voltage Pin, HV | HV | -0.3 |  | 500 | V |  | 4 |
| COMP, OTP, CS |  | -0.3 |  | 7 | V |  | 4 |
| OUT |  | -0.3 |  |  | V |  | 4 |
| Maximum Junction Temperature |  |  |  | 150 | °C |  | 4 |
| Operating Ambient Temperature |  | -40 |  | 85 | °C |  | 4 |
| Operating Junction Temperature |  | -40 |  | 125 | °C |  | 4 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 4 |
| Package Thermal Resistance (SOP-7/SOP-8) |  |  |  | 160 | °C/W | SOP-7/SOP-8 package | 4 |
| Power Dissipation (SOP-7/SOP-8) |  |  |  | 400 | mW | SOP-7/SOP-8, Ambient Temperature = 85°C | 4 |
| Lead temperature (Soldering, 10sec) |  |  |  | 260 | °C | Soldering, 10sec | 4 |
| ESD Voltage Protection, Human Body Model (except HV Pin) |  |  |  | 2.5 | KV | Human Body Model (except HV Pin) | 4 |
| ESD Voltage Protection, Machine Model |  |  |  | 250 | V | Machine Model | 4 |
| Gate Output Current |  |  |  | 500 | mA |  | 4 |
| High-Voltage Current Source |  | 0.5 | 1 | 1.5 | mA | VCC< UVLO(on), HV=500V | 5 |
| Off-State Leakage Current |  |  |  | 35 | μA | VCC> UVLO(off), HV=500V | 5 |
| Startup Current |  |  |  | 320 | μA |  | 5 |
| Operating Current |  |  |  | 1.2 | mA | with 1nF load on OUT pin; VCOMP=0V | 5 |
| Operating Current |  |  |  | 2.3 | mA | with 1nF load on OUT pin; VCOMP=3V | 5 |
| Operating Current |  |  |  | 0.6 | mA | with 1nF load on OUT pin; OLP tripped | 5 |
| Operating Current |  |  |  | 0.7 | mA | with 1nF load on OUT pin; OVP tripped, VCC=OVP | 5 |
| UVLO (off) |  | 9 | 10 | 11 | V |  | 5 |
| UVLO (on) |  | 15 | 16 | 17 | V |  | 5 |
| OVP Level |  | 25 | 26 | 27 | V |  | 5 |
| Short Circuit Current |  | 0.2 | 0.26 | 0.32 | mA | VCOMP=0V | 5 |
| Open Loop Voltage |  | 5.5 | 6 | 6.5 | V | COMP pin open | 5 |
| Green Mode Threshold | VCOMP |  | 2.75 |  | V |  | 5 |
| Zero Duty |  | 1.7 | 1.8 | 1.9 | V |  | 5 |
| Maximum Input Voltage, Vcs_off | Vcs_off | 0.8 | 0.85 | 0.9 | V |  | 5 |
| Leading Edge Blanking Time |  | 160 | 250 | 320 | ns |  | 5 |
| Input impedance |  |  | 1 |  | MΩ |  | 5 |
| Delay to Output |  |  | 100 |  | ns |  | 5 |
| Frequency |  | 61 | 65 | 69 | KHz |  | 5 |
| Green Mode Frequency |  |  | 22 |  | KHz |  | 5 |
| Trembling Frequency |  | -4 |  | 4 | kHz | VCOMP=4.5V | 5 |
| Temp. Stability |  |  |  | 5 | % | -20°C~85°C | 5 |
| Voltage Stability |  |  |  | 1 | % | VCC=11V-25V | 5 |
| OTP Pin Source Current |  | 92 | 100 | 108 | μA |  | 6 |
| Turn-On Trip Level |  | 1 | 1.05 | 1.1 | V |  | 6 |
| Turn-Off Trip Level |  | 0.9 | 0.95 | 1 | V |  | 6 |
| Output Low Level |  |  |  | 1 | V | VCC=15V, Io=20mA | 6 |
| Output High Level |  | 9 |  |  | V | VCC=15V, Io=20mA | 6 |
| Rising Time |  |  | 100 | 160 | ns | Load Capacitance=1000pF | 6 |
| Falling Time |  |  | 30 | 60 | ns | Load Capacitance=1000pF | 6 |
| OLP Trip Level |  | 4.8 | 5 | 5.2 | V |  | 6 |
| OLP Delay Time |  | 57 | 64 | 70 | ms |  | 6 |
| Soft Start Duration |  |  | 2 |  | ms |  | 6 |
| OTP Level |  |  | 140 |  | °C |  | 6 |
| OTP Hysteresis |  |  | 30 |  | °C |  | 6 |

## CAD (KiCad official)

- Symbol: `LD7750EGR`
- Footprint: `Package_SO:SOIC-8-N7_3.9x4.9mm_P1.27mm`
- 3D model: SOP-7 (KiCad packages3D, STEP)
- 3D model files: `ld7750egr-etched.step` / `ld7750egr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ld7750egr.step` / `ld7750egr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Leadtrend Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590230451345928192) (19 pp, sha256 `13824353fb043256`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ld7750egr-datasheet.pdf)