component
LD7552BPS
Public Made by Adomby adom
Leadtrend Tech AC-DC Controllers and Regulators, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLD7552BPS
Leadtrend Tech · AC-DC Controllers and Regulators · SOP-8
LD7552BPS from Leadtrend Tech, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Device ground return. Reference for VCC, gate driver source current, and current-sense signal. |
| 2 | COMP | input | Voltage feedback / loop compensation pin (equivalent to the COMP pin in UC384X). A secondary-side TL431 drives an opto-coupler that pulls this pin to close the regulation loop. Internal 6.0V open-loop voltage with 1/3 divider and 2 diode offsets feeds the PWM comparator. OLP trips when VCOMP exceeds 5.0V for >60ms (at 65kHz); pulling below 1.2V shuts off the output. |
| 3 | VCC | power_in | Supply voltage input (Abs Max 30V). UVLO turn-on 16V, turn-off 10V. OVP trips at 28.0V (auto-recovery, hiccup). Startup current <20µA; operating current ~2.0-3.0mA. Pin 3 and Pin 7 are internally the same VCC node. |
| 4 | RT | input | Oscillator programming pin. Connect a resistor from RT to GND to set the switching frequency: fSW(kHz) = 65 × 100kΩ / RT(kΩ). Recommended operating range 50-130kHz; typical 65kHz at RT=100kΩ. RT short-to-ground or RT-floating triggers fault protection. |
| 5 | NC | unconnected | No-connect pin. Leave floating or tie to GND per PCB-layout preference. |
| 6 | CS | input | Current-sense input from the primary MOSFET source resistor (Rs). Maximum threshold 0.85V (Ipeak_max = 0.85V / Rs). 350ns leading-edge blanking (LEB) suppresses turn-on spikes; 1MΩ input impedance, ~100ns delay to output. Abs Max -0.3 to +7V. Pin-floating triggers fault protection. |
| 7 | VCC | power_in | Supply voltage pin (same VCC net as pin 3). Bonded to pin 3 internally; both should be tied together at the VCC bypass capacitor to share bond-wire current for the 500mA gate driver. |
| 8 | OUT | output | CMOS gate-drive output for the external power MOSFET. Typical 500mA source/sink capability. Output-high ≈ VCC-6V (>9V at VCC=15V, Io=20mA); output-low <1V. Rise time ≈50ns, fall time ≈30ns into 1nF. Maximum duty cycle limited to 75% to prevent transformer saturation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Leadtrend Tech |
| Package | SOP-8 |
| Category | PMIC |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
LD7552BPSLD7552BPSGSLD7552BPSPN
CAD (KiCad official)
- Symbol:
LD7552BPS - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
ld7552bps-etched.step/ld7552bps-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ld7552bps.step/ld7552bps.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Leadtrend Tech datasheet (None pp, sha256
fff64f619363d956, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).