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LD59030DTPU18R

STMicroelectronics · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DFN-4(1x1)

LD59030DTPU18R from STMicroelectronics, in a DFN-4(1x1). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT power_out Regulated output voltage pin for the 1.8 V variant, which needs a ceramic output capacitor of at least 0.47 µF; the DT version adds an output discharge MOSFET (RON 120 Ω) that is active when EN is low.
2 GND power_in Common ground pin, to which all voltages are referenced; the thermal pad must also be connected to GND.
3 EN input Enable logic input where Low means shutdown and High means active, with logic low at most 0.4 V and logic high at least 1 V.
4 IN power_in Input voltage pin with an operating range of 1.5 V to 5.5 V, which needs an input capacitor of at least 1 µF placed close to the pin.
5 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package DFN-4(1x1)
Category Power Management (PMIC)
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VIN -0.3 7 V Referred to GND 5
Output voltage VOUT -0.3 V Max VIN + 0.3 V 5
Enable input voltage VEN -0.3 7 V Referred to GND 5
Storage temperature range TSTG -40 150 °C 5
Operating junction temperature range TOP -40 125 °C 5
Thermal resistance junction-ambient RthJA 140 °C/W 5
Operating input voltage VIN 1.5 5.5 V 6
VOUT accuracy VOUT -1 1 % IOUT = 1 mA, TJ = 25 °C 6
VOUT accuracy VOUT -2 2 % IOUT = 1 mA, -40 °C < TJ < 85 °C 6
Static line regulation ΔVOUT 0.05 %/V -40 °C < TJ < 85 °C 6
Static load regulation ΔVOUT -0.004 -0.01 %/mA IOUT = 0 mA to 300 mA, -40 °C < TJ < 85 °C 6
Dropout voltage VDROP 180 210 mV IOUT = 300 mA, VOUT = 1.8 V; typ at TJ = 25 °C, max at -40 °C < TJ < 85 °C (Table 6) 8
Quiescent current IQ 28 40 µA IOUT = 0 mA 6
Standby current IStandby 0.03 1 µA VEN = GND 6
Short circuit current ISC 120 170 mA VOUT = 0 (foldback protection) 6
Enable input logic low VEN 0.4 V VIN = 1.5 V to 5.5 V, -40 °C < TJ < 85 °C 6
Enable input logic high VEN 1 V VIN = 1.5 V to 5.5 V, -40 °C < TJ < 85 °C 6
Output capacitor COUT 0.47 22 µF Capacitance (see Figure 15. Stability area vs. (COUT, ESR)) 7

CAD (KiCad official)

  • Symbol: LD59030DTPU18R
  • Footprint: Package_DFN_QFN:UDFN-4-1EP_1x1mm_P0.65mm_EP0.48x0.48mm
  • 3D model: DFN-4(1x1) (KiCad packages3D, STEP)
  • 3D model files: ld59030dtpu18r-etched.step / ld59030dtpu18r-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ld59030dtpu18r.step / ld59030dtpu18r.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (24 pp, sha256 9d6692cfdb529f7b, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF