component

LD5762EGR

Public Made by Adom

by adom

Leadtrend Tech AC-DC Controllers & Regulators, SOP-7. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsld5762egrfactory-2.0.0extractor-text

Verified LD5762EGR

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier lcsc, 7 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: LD5762EGR · SOP-7 · 7 pins
  • ✓copper: 7 copper pads, none touching another net
  • ✓datasheet: all 7 pin names found in the 19-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: SOIC-8-N7_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-brr_ythu/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 7 pins = 7 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 7 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ld5762egr.kicad_sym✓ ld5762egr.kicad_mod✓ ld5762egr.step
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Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1d ago
viewers ld5762egr: viewers · Ray 1d ago
ld5762egr-etched.glb Publish 0.1.0 · Ray 1d ago
ld5762egr-etched.step ld5762egr: factory component page (tier=lcsc) · Ray 1d ago
ld5762egr-hero.glb ld5762egr: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
ld5762egr-hero.overlay.json Publish 0.1.0 · Ray 1d ago
ld5762egr.glb Publish 0.1.0 · Ray 1d ago
ld5762egr.kicad_mod Publish 0.1.0 · Ray 1d ago
ld5762egr.kicad_sym Publish 0.1.0 · Ray 1d ago
ld5762egr.lbr Publish 0.1.0 · Ray 1d ago
ld5762egr.step Publish 0.1.0 · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Publish 0.1.0 · Ray 1d ago
verification.json Verified: Published by the parts factory: tier lcsc, 7 pins · Ray 1d ago

LD5762EGR

Leadtrend Tech · AC-DC Controllers & Regulators · SOP-7

LD5762EGR from Leadtrend Tech, in a SOP-7. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 FB input Auxiliary voltage sense for output overvoltage protection (VFB_OVP trip at 3V) and quasi-resonant detection, with FB undervoltage protection triggered below 0.5V during gate-off.
2 COMP input Voltage feedback pin to connect a photo-coupler for closing the control loop, with COMP pulled below VZDC (1.95V typical) disabling the gate output.
3 CS input Current sense pin for the MOSFET current, with a maximum current-sense voltage threshold of 0.83V and a 300ns leading-edge blanking time.
4 GND power_in Ground reference for the controller.
5 OUT output Gate drive output that drives the external MOSFET, with output current rated +300mA/-800mA.
6 VCC power_in Supply voltage pin, with UVLO turn-on at 16V and turn-off at 6V and an OVP level of 28.5V typical.
8 HV input Connected to AC line/neutral through a resistor to provide startup current, with an internal divider monitoring AC line for brown-in/out and HV rated to 710V.

Key specifications

Parameter Value
Manufacturer Leadtrend Tech
Package SOP-7
Category Power Management ICs
Pins 7

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Junction Temperature -40 125 C 4
Supply VCC Voltage 8.5 26.5 V 4
HV resistor Value (AC Side) 8 17.5 K 4
HV to GND Capacitor Value 300 pF 4
Comp Pin Capacitor 1 10 nF 4
CS Pin Capacitor Value 47 390 pF 4
Supply Voltage VCC -0.3 30 V 4
HV pin voltage -0.3 710 V 4
COMP pin voltage -0.3 6 V 4
FB pin voltage -0.3 6 V 4
CS pin voltage -0.3 6 V 4
OUT pin voltage -0.3 V 4
Maximum Junction Temperature 150 C 4
Storage Temperature Range -65 150 C 4
Power Dissipation (SOP-8/SOP-7) 250 mW Ambient Temperature = 85C 4
Lead temperature (Soldering, 10sec) 260 C Soldering, 10sec 4
ESD Voltage Protection, Human Body Model (except HV pin) 2.5 KV Human Body Model, except HV pin 4
ESD Voltage Protection, Machine Model (except HV pin) 250 V Machine Model, except HV pin 4
ESD Voltage Protection, Human Body Model (HV pin) 1 KV Human Body Model, HV pin 4
ESD Voltage Protection, Machine Model (HV pin) 200 V Machine Model, HV pin 4
Gate Output Current -800 300 mA 4
HV Pin Brown-In Level (HVBI) VHVBO 95 105 115 VDC HV pin = half rectifier wave increase 5
HV Pin Brown-out Level (HVBO) VHVBI 82 92 102 VDC HV pin = half rectifier wave decrease 5
HV Pin BNO Hysteresis (HVBI-HVBO) ΔVHV 7 16 23 VDC 5
Brown-out Detection Delay time TD_HVBO 52 65 78 ms VCOMP=3V 5
X-Cap discharge Detection Delay time TD_XCAP 52 65 78 ms VCOMP=3V 5
UVLO(OFF) VCC_OFF 5.5 6 6.5 V 5
UVLO(ON) VCC_ON 15 16 17 V 5
VCC OVP Level VCC_OVP 27.5 28.5 29.5 V 5
Frequency FSW_N 61 65 69 KHz VCOMP=3V 6
Green Mode Frequency FSW_GREEN 22 25 28 KHz With Fsw swapping 6
FSW Temp. Stability FSW_TS 0 3 4 % -40C ~105C 6
Maximum On Time DMAX 78 83 88 % 6
Open Loop Voltage VCOMP_OPEN 4.9 5.2 5.5 V COMP pin open 6
OCP Tripped Level VOCP 4.4 4.6 4.8 V TC: track COMP pin open voltage 6
Zero Duty Threshold VCOMP on Burst mode VZDC 1.85 1.95 2.05 V Zero Duty (Fig 1.) 6
OCP Compensation Current (IOCP_20_H) IOCP_20_H 225 240 255 A 6
OCP Delay Time TD_OCP 62 76 90 ms 6
Limit Voltage VCS_MAX 0.79 0.83 0.87 V 6
Output High Level VOH 8 V VCC=15V, Io=20mA 7
UVP Trip voltage Level VFB_UVP 0.45 0.5 0.55 V VAC> 250 VDC 7
OVP Trip voltage Level VFB_OVP 2.85 3 3.15 V 7
OTP Trip Current Level VCSOTP 0.43 0.45 0.47 V 7
Package Thermal Resistance (SOP-8/SOP-7) 160 C/W 4

CAD (KiCad official)

  • Symbol: LD5762EGR
  • Footprint: Package_SO:SOIC-8-N7_3.9x4.9mm_P1.27mm
  • 3D model: SOP-7 (KiCad packages3D, STEP)
  • 3D model files: ld5762egr-etched.step / ld5762egr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ld5762egr.step / ld5762egr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Leadtrend Tech datasheet (19 pp, sha256 818e1573b2f1a8bd, retrieved 2026-11-05, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF