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LD501PCSOT-33

analogysemi · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT23-5

LD501PCSOT-33 from analogysemi, in a SOT23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VIN	power_in	Regulator input supply (2.2V to 5.5V); bypass VIN to GND with a 1μF or greater capacitor.
2	GND	power_in	Ground.
3	EN	input	Enable input; drive high to turn on the regulator and low to turn it off, connect to VIN for automatic startup, and do not leave floating.
4	NC	unconnected	No connect; not connected internally.
5	VOUT	power_out	Regulated 3.3V output voltage (250mA max for LD501P); bypass VOUT to GND with a 1μF or greater capacitor.

Key specifications

Parameter	Value
Manufacturer	analogysemi
Package	SOT23-5
Category	Power Management (PMIC)
Pins	5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VIN to GND	VIN	-0.3		6.5	V		6
VOUT to GND	VOUT	-0.3			V	max printed as VIN	6
EN to GND	EN	-0.3		6.5	V		6
Operating temperature	TA	-40		125	°C		6
Junction temperature	TJ	-40		125	°C		6
Storage temperature	Tstg	-65		150	°C		6
ESD HBM	V(ESD)	-5000		5000	V	Human-body model, ANSI/ESDA/JEDEC JS-001	6
ESD CDM	V(ESD)	-2000		2000	V	Charged-device model, JESD22-C101	6
Input voltage range	VIN	2.2		5.5	V		7
Output current range LD501P	IOUT	0		250	mA	LD501P	7
EN voltage	VEN	0			V	max printed as VIN	7
Output capacitor	COUT	0.7	1		µF		7
Output capacitor ESR	RESR	0.001		0.2	Ω		7
Junction temperature	TJ	-40		125	°C		7
Junction-to-ambient thermal resistance	RθJA		168		°C/W	SOT23-5	7
Junction-to-case (top) thermal resistance	RθJC(top)		103		°C/W	SOT23-5	7
Junction-to-board thermal resistance	RθJB		39		°C/W	SOT23-5	7
Junction-to-top characterization parameter	ψJT		10		°C/W	SOT23-5	7
Junction-to-board characterization parameter	ψJB		36		°C/W	SOT23-5	7
Junction-to-case (bottom) thermal resistance	RθJC(bot)		66		°C/W	SOT23-5	7
Input voltage range	VIN	2.2		5.5	V	TJ = −40°C to 125°C	8
Operating supply current	IGND		12	25	μA	IOUT = 0μA; max at TJ = −40°C to 125°C	8
Operating supply current	IGND		28	54	μA	IOUT = 100μA; max at TJ = −40°C to 125°C	8
Operating supply current	IGND		61	100	μA	IOUT = 10mA; max at TJ = −40°C to 125°C	8
Operating supply current	IGND		229	291	μA	IOUT = 250mA; max at TJ = −40°C to 125°C	8
Shutdown current	IGND-SD		0.25	1.8	μA	EN = GND; max at TJ = −40°C to 125°C	8
Output voltage accuracy	VOUT	-1		1	%	IOUT = 10mA	8
Output voltage accuracy	VOUT	-2.5		1.5	%	TJ = −40°C to 125°C, VOUT ≥1.8V, 100μA < IOUT < 250mA, VIN = (VOUT + 0.4V) to 5.5V	8
Load regulation	∆VOUT/∆IOUT		0.002	0.005	%/mA	VOUT ≥ 1.8V, IOUT = 100μA to 250mA; max at TJ = −40°C to 125°C	8
Line regulation	∆VOUT/∆VIN		0.02		%/V	VIN = (VOUT + 0.4V) to 5.5V, TJ = −40°C to 125°C	8
Dropout voltage	VDROPOUT		118	117	mV	IOUT = 250mA; max at TJ = −40°C to 125°C	9
Current-limit threshold	ILIMIT	260	350	385	mA	TJ = 0°C to 125°C, LD501P	9
Start-up time	tSTART-UP		180		µs	VOUT = 3.3V	9
UVLO input voltage rising	UVLORISE		2.1		V	TJ = −40°C to 125°C	9
UVLO input voltage falling	UVLOFALL		1.75	2	V	TJ = −40°C to 125°C	9
UVLO hysteresis	UVLOHYS		102		mV	TJ = −40°C to 125°C	9
Thermal shutdown threshold	TSSD		155		°C	TJ rising	9
Thermal shutdown hysteresis	TSSD-HYS		20		°C	TJ rising	9
EN input logic high	VIH	1.2			V	2.2V ≤ VIN ≤ 5.5V	9
EN input logic low	VIL			0.4	V	2.2V ≤ VIN ≤ 5.5V	9
EN input leakage current	IEN		0.001		µA	VIN = VEN = 5.5V	9
Output noise	OUTNOISE		13.5		μV rms	10Hz to 100kHz, VIN = 5V, VOUT = 3.3V	9
PSRR	PSRR		74		dB	10kHz, VIN = 3.8V, VOUT = 3.3V, IOUT = 10mA	9
PSRR	PSRR		57		dB	100kHz, VIN = 3.8V, VOUT = 3.3V, IOUT = 10mA	9
PSRR	PSRR		71		dB	10kHz, VIN = 4.3V, VOUT = 3.3V, IOUT = 10mA	9
PSRR	PSRR		58		dB	100kHz, VIN = 4.3V, VOUT = 3.3V, IOUT = 10mA	9

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts	copper		to solder the package GND pins to the PCB. Table 9 shows typical θJA values of the SOT23-5 for various PCB copper sizes. Table 10 shows the typical ΨJB	19

CAD (KiCad official)

Symbol: LD501PCSOT-33
Footprint: Package_TO_SOT_SMD:SOT-23-5
3D model: SOT23-5 (KiCad packages3D, STEP)
3D model files: ld501pcsot-33-etched.step / ld501pcsot-33-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ld501pcsot-33.step / ld501pcsot-33.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: analogysemi datasheet (24 pp, sha256 6b45c64f53dc3063, retrieved 2026-10-27, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF