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LD1117DT33TR

Public Made by Adom

by adom

STMicroelectronics Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, TO-252-2. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs ld1117dt33tr: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain S… · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
ld1117dt33tr-etched.fit.json ld1117dt33tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
ld1117dt33tr-etched.glb ld1117dt33tr: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain S… · Ray
ld1117dt33tr-etched.step ld1117dt33tr: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain S… · Ray
ld1117dt33tr.glb Publish 0.1.0 · Ray
ld1117dt33tr.kicad_mod Publish 0.1.0 · Ray
ld1117dt33tr.kicad_sym Publish 0.1.0 · Ray
ld1117dt33tr.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
ld1117dt33tr.step Publish 0.1.0 · Ray
package.json Publish 0.2.0 · Ray
pads.json page.json: fold the "TAB" entry into pin 2. On TO-252-2 the tab is not a separate pad - it is that lead - so nothing wa… · Ray
page.json ld1117dt33tr: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain S… · Ray
README.md ld1117dt33tr: specified limits as data (metadata.characteristics, 20 rows from the datasheet) · Ray

LD1117DT33TR

STMicroelectronics · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · TO-252-2

LD1117DT33TR from STMicroelectronics, in a TO-252-2. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground / common return. Reference for both the input and 3.3 V output.
2 VOUT power_out Regulated 3.3 V output, up to 800 mA. Requires a 10 µF minimum output capacitor for loop stability. Electrically tied to the DPAK TAB.
3 VIN power_in Unregulated DC input, 4.3 V to 15 V typical (absolute max 15 V continuous, 18 V with IOUT < 20 mA). A 100 nF input decoupling capacitor is recommended.
TAB VOUT power_out DPAK metal tab, electrically connected to VOUT. Serves as the primary heat-sinking path (RthJC = 8 °C/W).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package TO-252-2
Category PMIC
Pins 4

Ordering variants

Same part, different packaging or reel option.

  • LD1117DT33TR
  • LD1117DT33-TR
  • LD1117DT33TRS33TR
  • LD1117DT33TRD33TR
  • LD1117DT33TRV33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output voltage (Vin = 5.3 V, IO = 10 mA, TJ = 25 °C) VO 3.267 3.3 3.333 V Vin = 5.3 V, IO = 10 mA, TJ = 25 °C 12
Output voltage (IO = 0 to 800 mA) VO 3.235 3.365 V IO = 0 to 800 mA, Vin = 4.75 to 10 V 12
Line regulation ΔVO 1 6 mV Vin = 4.75 to 15 V, IO = 0 mA 12
Load regulation ΔVO 1 10 mV Vin = 4.75 V, IO = 0 to 800 mA 12
Quiescent current Id 5 10 mA Vin ≤ 15 V 12
Output current IO 800 950 1300 mA Vin = 8.3 V, TJ = 25 °C 12
Supply voltage rejection SVR 60 75 dB IO = 40 mA, f = 120 Hz, TJ = 25 °C, Vin = 6.3 V, Vripple = 1 VPP 12
Dropout voltage (100 mA) Vd 1 1.1 V IO = 100 mA 12
Dropout voltage (500 mA) Vd 1.05 1.15 V IO = 500 mA 12
Dropout voltage (800 mA) Vd 1.1 1.2 V IO = 800 mA 12
Thermal regulation 0.01 0.1 %/W Ta = 25 °C, 30 ms pulse 12
Operating input voltage Vin 15 V IO = 100 mA 12
Temperature stability ΔVO 0.5 % 12
Long term stability ΔVO 0.3 % 1000 hrs, TJ = 125 °C 12
Input voltage (DC, absolute maximum) VIN 15 V Footnote 1: VIN = 18 V absolute maximum when IOUT is lower than 20 mA 7
Power dissipation PTOT 12 W 7
Storage temperature range TSTG -40 150 °C 7
Operating junction temperature range TOP 0 125 °C Standard version 7
Thermal resistance junction-case (DPAK) RthJC 8 °C/W DPAK 7
Thermal resistance junction-ambient (DPAK) RthJA 100 °C/W DPAK 7

CAD (KiCad official)

  • Symbol: LD1117DT33TR
  • Footprint: Package_TO_SOT_SMD:TO-252-2
  • 3D model: TO-252-2 (KiCad packages3D, STEP)
  • 3D model files: ld1117dt33tr-etched.step / ld1117dt33tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ld1117dt33tr.step / ld1117dt33tr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
ld1117dt33tr.step 119 KB You want the bare part, or you mark your own boards.
ld1117dt33tr-etched.step 1.7 MB You want the part with LD1117DT33TR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 464 faces against 83 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (44 pp, sha256 1b80923ec6ca9161, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF