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Initial commit: component/ld1117dt18tr

Ray ·a5d177b8be ·16h ago
2 files changed +209
README.mdadded+39
@@ -0,0 +1,39 @@+# LD1117DT18TR++**STMicroelectronics** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DPAK++LD1117DT18TR from STMicroelectronics, in a DPAK. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GND | power_in | Labelled ADJ/GND in the pin diagram; on the fixed 1.8 V LD1117DT18TR this is the ground reference pin (it is the adjustment pin only on the adjustable version). |+| 2 | VOUT | power_out | Regulated output (1.8 V fixed, up to 800 mA output current, needs a 10 µF minimum output capacitor for stability); the TAB is connected to VOUT. |+| 3 | VIN | power_in | Input supply voltage, with absolute maximum DC input of 15 V (18 V when IOUT is lower than 20 mA). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | DPAK |+| Category | Power Management (PMIC) |+| Pins | 3 |++## CAD (KiCad official)++- Symbol: `LD1117DT18TR`+- Footprint: `Package_TO_SOT_SMD:TO-252-2`+- 3D model: DPAK (KiCad packages3D, STEP)+- 3D model files: `ld1117dt18tr-etched.step` / `ld1117dt18tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ld1117dt18tr.step` / `ld1117dt18tr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590295138561404928) (46 pp, sha256 `eb9bdaeee6a99a12`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ld1117dt18tr-datasheet.pdf)
page.jsonadded+170
@@ -0,0 +1,170 @@+{+  "slug": "ld1117dt18tr",+  "version": "0.1.0",+  "type": "component",+  "description": "STMicroelectronics Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, DPAK. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "power management (pmic)",+    "ld1117dt18tr",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "ld1117dt18tr.kicad_sym",+    "ld1117dt18tr.kicad_mod",+    "ld1117dt18tr.glb",+    "ld1117dt18tr.step",+    "ld1117dt18tr.lbr",+    "docs/hero.png",+    "docs/ld1117dt18tr-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html",+    "ld1117dt18tr-hero.glb",+    "ld1117dt18tr-hero.overlay.json"+  ],+  "component": {+    "mpn": "LD1117DT18TR",+    "manufacturer": "STMicroelectronics",+    "package": "DPAK",+    "pin_count": 3,+    "category": "Power Management (PMIC)",+    "subcategory": "Voltage Regulators - Linear, Low Drop Out (LDO) Regulators",+    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590295138561404928",+    "parts": {+      "symbol": "ld1117dt18tr.kicad_sym",+      "footprint": "ld1117dt18tr.kicad_mod",+      "model_3d": "ld1117dt18tr-hero.glb",+      "model_3d_plain": "ld1117dt18tr.glb",+      "model_3d_step": "ld1117dt18tr-etched.step",+      "model_3d_step_plain": "ld1117dt18tr.step",+      "lbr": "ld1117dt18tr.lbr"+    },+    "distributor_links": {+      "lcsc": "C2970384",+      "digikey": "497-1232-2-ND",+      "mouser": "511-LD1117DT18-TR"+    },+    "distributor_check": {+      "checked_at": "2026-10-08T02:44:22Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "497-1232-2-ND",+        "status": "found"+      },+      "mouser": {+        "pn": "511-LD1117DT18-TR",+        "status": "found"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "GND",+        "type": "power_in",+        "description": "Labelled ADJ/GND in the pin diagram; on the fixed 1.8 V LD1117DT18TR this is the ground reference pin (it is the adjustment pin only on the adjustable version)."+      },+      {+        "number": "2",+        "name": "VOUT",+        "type": "power_out",+        "description": "Regulated output (1.8 V fixed, up to 800 mA output current, needs a 10 µF minimum output capacitor for stability); the TAB is connected to VOUT."+      },+      {+        "number": "3",+        "name": "VIN",+        "type": "power_in",+        "description": "Input supply voltage, with absolute maximum DC input of 15 V (18 V when IOUT is lower than 20 mA)."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.3",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.3",+        "primary_model": "claude-sonnet-5-5",+        "primary_mode": "text+vision",+        "consensus_model": "claude-opus-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [+          "extractor flagged: The pin diagram labels pin 1 as ADJ/GND for all variants. I assigned it as GND because LD1117DT18TR ; The DPAK tab is connected to VOUT per the note. It has no pin number in the diagram, so I did not li",+          "vision extraction: provenance cannot be text-verified; needs consensus"+        ],+        "pages_sent": 46,+        "cost_usd": 0.3413,+        "at": "2026-10-08T02:44:06"+      },+      "datasheet": {+        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590295138561404928",+        "pages": 46,+        "sha256": "eb9bdaeee6a99a12",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 3,+        "described": 3,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    },+    "models_3d": [+      {+        "file": "ld1117dt18tr.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          9.9,+          6.5,+          2.32+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "3eb4c99603a4fe837c2fe9308bc174769ded87a785a0df48d2dc441432ee8b4c",+        "checked": "2026-10-08",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "ld1117dt18tr-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          9.9,+          6.5,+          2.32+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "82b57017d20ef1a78988a8c8abe2b0438a3867b72c033a1b541973259fc60724",+        "checked": "2026-10-08",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      }+    ]+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file