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Contents

README

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LD1117DT18TR

STMicroelectronics · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DPAK

LD1117DT18TR from STMicroelectronics, in a DPAK. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Labelled ADJ/GND in the pin diagram; on the fixed 1.8 V LD1117DT18TR this is the ground reference pin (it is the adjustment pin only on the adjustable version).
2 VOUT power_out Regulated output (1.8 V fixed, up to 800 mA output current, needs a 10 µF minimum output capacitor for stability); the TAB is connected to VOUT.
3 VIN power_in Input supply voltage, with absolute maximum DC input of 15 V (18 V when IOUT is lower than 20 mA).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package DPAK
Category Power Management (PMIC)
Pins 3

CAD (KiCad official)

  • Symbol: LD1117DT18TR
  • Footprint: Package_TO_SOT_SMD:TO-252-2
  • 3D model: DPAK (KiCad packages3D, STEP)
  • 3D model files: ld1117dt18tr-etched.step / ld1117dt18tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ld1117dt18tr.step / ld1117dt18tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (46 pp, sha256 eb9bdaeee6a99a12, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF