component

LD1117AS33TR

Public Made by Adom

by adom

STMicroelectronics Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-223-4. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

componentpmicld1117as33tr
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
Name Last commit message Last updated
docs ld1117as33tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
ld1117as33tr-etched.fit.json ld1117as33tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
ld1117as33tr-etched.glb ld1117as33tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
ld1117as33tr-etched.step ld1117as33tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
ld1117as33tr.glb Publish 0.1.0 · Ray 1mo ago
ld1117as33tr.kicad_mod fix footprint: SOT-223-3_TabPin2 -> SOT-223 (pad_count, 4 pins) · Ray 1mo ago
ld1117as33tr.kicad_sym Publish 0.1.0 · Ray 1mo ago
ld1117as33tr.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 4 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray 1mo ago
ld1117as33tr.step Publish 0.1.0 · Ray 1mo ago
package.json Publish 0.2.0 · Ray 1mo ago
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
page.json ld1117as33tr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1d ago
README.md ld1117as33tr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 19d ago

LD1117AS33TR

STMicroelectronics · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-223-4

LD1117AS33TR from STMicroelectronics, in a SOT-223-4. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ADJ/GND power_in Ground reference pin for the fixed 3.3 V version (labeled ADJ/GND because the same die is used for the adjustable variant). Tie directly to system ground for the LD1117AS33TR. Quiescent current is typically 5 mA.
2 VOUT power_out Regulated 3.3 V output (typ 3.3 V, 3.234-3.366 V at 25 °C, 10 mA). Sources up to 1 A (min 1000 mA, typ 1200 mA short-circuit). Requires a ≥10 µF output capacitor for loop stability. Internally connected to the exposed metal tab.
3 VIN power_in Unregulated DC input supply. Operating input voltage up to 10 V (absolute max 15 V). Minimum VIN for 3.3 V regulation is ~4.75 V (dropout typ 1.15 V at 1 A). A 100 nF input decoupling capacitor is recommended.
4 TAB power_out Large SOT-223 heat-sink tab, internally shorted to VOUT. Provides the primary thermal path (RthJC = 15 °C/W); should be soldered to a copper area on the PCB that is also the VOUT net.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SOT-223-4
Category PMIC
Pins 4

Ordering variants

Same part, different packaging or reel option.

  • LD1117AS33TR
  • LD1117AS33TRASTR
  • LD1117AS33TRAS12TR
  • LD1117AS33TRAS18TR
  • LD1117AS33TRADT33TR
  • LD1117AS33TRADT-TR
  • LD1117AS33TRADT12TR
  • LD1117AS33TRADT18TR
  • LD1117AS33TRAV33

CAD (KiCad official)

  • Symbol: LD1117AS33TR
  • Footprint: Package_TO_SOT_SMD:SOT-223
  • 3D model: SOT-223-4 (KiCad packages3D, STEP)
  • 3D model files: ld1117as33tr-etched.step / ld1117as33tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ld1117as33tr.step / ld1117as33tr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
ld1117as33tr.step 64 KB You want the bare part, or you mark your own boards.
ld1117as33tr-etched.step 1.9 MB You want the part with LD1117AS33TR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 482 faces against 75 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (24 pp, sha256 c2dd41daa75f2827, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF