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LD1117AS18TR

Public Made by Adom

by adom

STMicroelectronics Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-223-3. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
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docs ld1117as18tr: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain S… · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
ld1117as18tr-etched.fit.json ld1117as18tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
ld1117as18tr-etched.glb ld1117as18tr: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain S… · Ray
ld1117as18tr-etched.step ld1117as18tr: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain S… · Ray
ld1117as18tr-hero.glb Publish 0.2.1 · Ray
ld1117as18tr-hero.overlay.json Publish 0.2.1 · Ray
ld1117as18tr.glb Publish 0.1.0 · Ray
ld1117as18tr.kicad_mod Publish 0.1.0 · Ray
ld1117as18tr.kicad_sym Publish 0.1.0 · Ray
ld1117as18tr.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
ld1117as18tr.step Publish 0.1.0 · Ray
package.json Publish 0.2.1 · Ray
pads.json page.json: fold the "TAB" entry into pin 2. On SOT-223-3_TabPin2 the tab is not a separate pad - it is that lead - so n… · Ray
page.json Publish 0.2.1 · Ray
README.md ld1117as18tr: specified limits as data (metadata.characteristics, 21 rows from the datasheet) · Ray

LD1117AS18TR

STMicroelectronics · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-223-3

LD1117AS18TR from STMicroelectronics, in a SOT-223-3. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ADJ/GND power_in Ground reference pin for the fixed-output versions (LD1117AS18 uses this pin as GND). On the adjustable variant this same pin is the ADJ feedback input (VREF = 1.25 V to the external divider). Connect to system ground for the LD1117AS18TR (1.8 V fixed).
2 VOUT power_out Regulated 1.8 V output. Sources up to 1 A (1.2 A typical current limit). Requires a minimum 10 µF output capacitor to GND for loop stability. The SOT-223 tab is internally connected to this pin.
3 VIN power_in Unregulated DC input supply. Operating input voltage up to 10 V (absolute max 15 V). Dropout ≤1.15 V typ at 1 A, so VIN must be ≥ VOUT + VDROPOUT. A 100 nF input capacitor is recommended close to the pin.
TAB VOUT power_out SOT-223 thermal tab, internally shorted to the VOUT pin (pin 2). Provides the primary heat-sinking path (RthJC = 15 °C/W, RthJA = 110 °C/W). Solder to a copper pour tied to VOUT to improve thermal performance.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SOT-223-3
Category PMIC
Pins 4

Ordering variants

Same part, different packaging or reel option.

  • LD1117AS18TR
  • LD1117ADT18TR
  • LD1117AV33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output voltage VO 1.764 1.8 1.836 V VI = 3.8 V, IO = 10 mA, TJ = 25 °C 7
Output voltage VO 1.728 1.872 V IO = 0 to 1 A, VI = 3.3 to 8 V 7
Line regulation ΔVO 1 6 mV VI = 3.3 to 8 V, IO = 0 mA 7
Load regulation ΔVO 1 10 mV VI = 3.3 V, IO = 0 to 1 A 7
Temperature stability ΔVO 0.5 % 7
Long term stability ΔVO 0.3 % 1000 hrs, TJ = 125 °C 7
Operating input voltage VI 10 V IO = 100 mA 7
Quiescent current Id 5 10 mA VI ≤ 8 V, IO = 0 mA 7
Output current IO 1000 mA VI - VO = 5 V, TJ = 25 °C 7
Output noise voltage eN 100 µV B = 10 Hz to 10 kHz, TJ = 25 °C 8
Supply voltage rejection SVR 60 80 dB IO = 40 mA, f = 120 Hz, VI - VO = 3 V, Vripple = 1 VPP 8
Dropout voltage VD 1 1.1 V IO = 100 mA 8
Dropout voltage VD 1.05 1.15 V IO = 500 mA 8
Dropout voltage VD 1.15 1.3 V IO = 1 A 8
Thermal regulation ΔVO(pwr) 0.08 0.2 %/W Ta = 25 °C, 30 ms pulse 8
DC input voltage VIN 15 V 5
Power dissipation PD 12 W 5
Storage temperature range TSTG -40 150 °C 5
Operating junction temperature range TOP 0 125 °C 5
Thermal resistance junction-case, SOT-223 RthJC 15 °C/W 5
Thermal resistance junction-ambient, SOT-223 RthJA 110 °C/W 5

CAD (KiCad official)

  • Symbol: LD1117AS18TR
  • Footprint: Package_TO_SOT_SMD:SOT-223-3_TabPin2
  • 3D model: SOT-223-3 (KiCad packages3D, STEP)
  • 3D model files: ld1117as18tr-etched.step / ld1117as18tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ld1117as18tr.step / ld1117as18tr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
ld1117as18tr.step 64 KB You want the bare part, or you mark your own boards.
ld1117as18tr-etched.step 1.8 MB You want the part with LD1117AS18TR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 454 faces against 75 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (24 pp, sha256 5cf3aab5b1478366, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF