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LD1117-1.8

Public Made by Adom

by adom

UMW Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-223. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
Name Last commit message Last updated
docs ld1117-1-8: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain STE… · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
ld1117-1-8-etched.fit.json ld1117-1-8: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
ld1117-1-8-etched.glb ld1117-1-8: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain STE… · Ray
ld1117-1-8-etched.step ld1117-1-8: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain STE… · Ray
ld1117-1-8-hero.glb Publish 0.2.1 · Ray
ld1117-1-8-hero.overlay.json Publish 0.2.1 · Ray
ld1117-1-8.glb Publish 0.1.0 · Ray
ld1117-1-8.kicad_mod Publish 0.1.0 · Ray
ld1117-1-8.kicad_sym Publish 0.1.0 · Ray
ld1117-1-8.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
ld1117-1-8.step Publish 0.1.0 · Ray
package.json Publish 0.2.1 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json Publish 0.2.1 · Ray
README.md ld1117-1-8: specified limits as data (metadata.characteristics, 14 rows from the datasheet) · Ray

LD1117-1.8

UMW · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-223

LD1117-1.8 from UMW, in a SOT-223. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground reference for the fixed-output LD1117-1.8. On the adjustable LD1117-ADJ this same pin functions as the ADJ feedback node (VREF=1.25V nominal); on fixed versions the internal F1/F2 divider is connected and the ADJ path (A) is disconnected, so the pin is a plain ground return.
2 VOUT power_out Regulated 1.8V output (1.764V min / 1.836V max at IOUT=10mA, VIN=3.8V, TJ=25°C). Delivers up to 1A continuous with typical dropout of 1.2V at 1A. Requires an output capacitor for stability; internally protected by current limit (1.25-1.6A) and thermal shutdown (~150°C).
3 VIN power_in Unregulated input supply. Absolute maximum 18V; recommended operating input ≤12V. Must exceed VOUT by at least the dropout voltage (≥1.2V at 1A) to remain in regulation. Bypass with a bulk input capacitor.

Key specifications

Parameter Value
Manufacturer UMW
Package SOT-223
Category PMIC
Pins 3

Ordering variants

Same part, different packaging or reel option.

  • LD1117-1.8
  • LD1117-1.8CD
  • LD1117-1.8S

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output Voltage (LD1117-1.8) VOUT 1.764 1.8 1.836 V IOUT=10mA, VIN=3.8V, TJ=25°C 4
Line Regulation Rline 9 18 mV VINMIN ≤VIN≤ 12V, VOUT=Fixed/Adj, IOUT=10mA 4
Quiescent Current Iq 5 10 mA 5
Adjust pin Current Iadj 60 120 µA 5
Adjust pin Current Change 0.2 5 µA 0≤ IOUT≤1A, 1.4V ≤VIN-VOUT≤10V 5
Ripple Rejection PSRR 60 75 dB fRIPPLE=120Hz, (VIN-VOUT)=3V, VRIPPLE=1VPP 5
Input Supply Voltage VIN 18 V 3
Lead Temperature (Soldering, 5 seconds) TLead 260 °C Soldering, 5 seconds 3
Junction Temperature Range TJ 150 °C 3
Storage Temperature Range TSTG -65 150 °C 3
ESD Tolerance (Minimum) ESD 2000 V 3
Thermal Resistance from Junction to Ambient (SOT-223) Rja 88 °C/W 3
Input voltage VIN 12 V 3
Junction Temperature Range TJ -40 125 °C 3

CAD (KiCad official)

  • Symbol: LD1117-1.8
  • Footprint: Package_TO_SOT_SMD:SOT-223-3_TabPin2
  • 3D model: SOT-223 (KiCad packages3D, STEP)
  • 3D model files: ld1117-1-8-etched.step / ld1117-1-8-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ld1117-1-8.step / ld1117-1-8.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
ld1117-1-8.step 64 KB You want the bare part, or you mark your own boards.
ld1117-1-8-etched.step 1.2 MB You want the part with LD1117-1.8 already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 322 faces against 75 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: UMW datasheet (14 pp, sha256 b65a8249b6e9e313, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF