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LCMXO640C-3TN144I

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Lattice CPLD/FPGA, TQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LCMXO640C-3TN144I

Lattice · CPLD/FPGA · TQFP-144(20x20)

LCMXO640C-3TN144I from Lattice, in a TQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PL2A bidirectional User I/O, Bank 3, differential true (T) of the pair.
2 PL2C bidirectional User I/O, Bank 3, differential true (T) of the pair.
3 PL2B bidirectional User I/O, Bank 3, differential complement (C) of the pair.
4 PL3A bidirectional User I/O, Bank 3, differential true (T) of the pair.
5 PL2D bidirectional User I/O, Bank 3, differential complement (C) of the pair.
6 PL3B bidirectional User I/O, Bank 3, differential complement (C) of the pair.
7 PL3C bidirectional User I/O, Bank 3, differential true (T) of the pair.
8 PL3D bidirectional User I/O, Bank 3, differential complement (C) of the pair.
9 PL4A bidirectional User I/O, Bank 3.
10 VCCIO3 power_in Power supply pin for I/O Bank 3.
11 GNDIO3 power_in Ground for I/O Bank 3.
12 PL4D bidirectional User I/O, Bank 3.
13 PL5A bidirectional User I/O, Bank 3, differential true (T) of the pair.
14 PL5B bidirectional User I/O, Bank 3, dual function GSRN (active-low global reset input), differential complement (C).
15 PL5D bidirectional User I/O, Bank 3.
16 GND power_in Ground, dedicated pin; all grounds must be connected at board level.
17 PL6C bidirectional User I/O, Bank 3, differential true (T) of the pair.
18 PL6D bidirectional User I/O, Bank 3, differential complement (C) of the pair.
19 PL7A bidirectional User I/O, Bank 3, differential true (T) of the pair.
20 PL7B bidirectional User I/O, Bank 3, differential complement (C) of the pair.
21 VCC power_in Core logic power supply, dedicated pin.
22 PL8A bidirectional User I/O, Bank 3, differential true (T) of the pair.
23 PL8B bidirectional User I/O, Bank 3, differential complement (C) of the pair.
24 PL8C bidirectional User I/O, Bank 3, dual function TSALL (global output enable; all outputs tristated when high).
25 PL9C bidirectional User I/O, Bank 3, differential true (T) of the pair.
26 VCCIO3 power_in Power supply pin for I/O Bank 3.
27 GNDIO3 power_in Ground for I/O Bank 3.
28 PL9D bidirectional User I/O, Bank 3, differential complement (C) of the pair.
29 PL10A bidirectional User I/O, Bank 3, differential true (T) of the pair.
30 PL10B bidirectional User I/O, Bank 3, differential complement (C) of the pair.
31 PL10C bidirectional User I/O, Bank 3, differential true (T) of the pair.
32 PL11A bidirectional User I/O, Bank 3, differential true (T) of the pair.
33 PL10D bidirectional User I/O, Bank 3, differential complement (C) of the pair.
34 PL11C bidirectional User I/O, Bank 3, differential true (T) of the pair.
35 PL11B bidirectional User I/O, Bank 3, differential complement (C) of the pair.
36 PL11D bidirectional User I/O, Bank 3, differential complement (C) of the pair.
37 GNDIO2 power_in Ground for I/O Bank 2.
38 VCCIO2 power_in Power supply pin for I/O Bank 2.
39 TMS input JTAG Test Mode Select input controlling the 1149.1 state machine.
40 PB2C bidirectional User I/O, Bank 2.
41 PB3A bidirectional User I/O, Bank 2, differential true (T) of the pair.
42 TCK input JTAG Test Clock input clocking the 1149.1 state machine.
43 PB3B bidirectional User I/O, Bank 2, differential complement (C) of the pair.
44 PB3C bidirectional User I/O, Bank 2, differential true (T) of the pair.
45 PB3D bidirectional User I/O, Bank 2, differential complement (C) of the pair.
46 PB4A bidirectional User I/O, Bank 2, differential true (T) of the pair.
47 TDO output JTAG Test Data output shifting data out of the device.
48 PB4B bidirectional User I/O, Bank 2, differential complement (C) of the pair.
49 PB4C bidirectional User I/O, Bank 2, differential true (T) of the pair.
50 PB4D bidirectional User I/O, Bank 2, differential complement (C) of the pair.
51 TDI input JTAG Test Data input used to load data into the device.
52 VCC power_in Core logic power supply, dedicated pin.
53 VCCAUX power_in Auxiliary power supply powering internal circuits including differential and referenced input buffers.
54 PB5A bidirectional User I/O, Bank 2, differential true (T) of the pair.
55 PB5B bidirectional User I/O, Bank 2, dual function primary clock input PCLKT2_1 (single-ended), differential complement (C).
56 PB5D bidirectional User I/O, Bank 2.
57 PB6A bidirectional User I/O, Bank 2, differential true (T) of the pair.
58 PB6B bidirectional User I/O, Bank 2, dual function primary clock input PCLKT2_0 (single-ended), differential complement (C).
59 GND power_in Ground, dedicated pin; all grounds must be connected at board level.
60 PB7C bidirectional User I/O, Bank 2.
61 PB7E bidirectional User I/O, Bank 2.
62 PB8A bidirectional User I/O, Bank 2.
63 VCCIO2 power_in Power supply pin for I/O Bank 2.
64 GNDIO2 power_in Ground for I/O Bank 2.
65 PB8C bidirectional User I/O, Bank 2, differential true (T) of the pair.
66 PB8D bidirectional User I/O, Bank 2, differential complement (C) of the pair.
67 PB9A bidirectional User I/O, Bank 2, differential true (T) of the pair.
68 PB9C bidirectional User I/O, Bank 2, differential true (T) of the pair.
69 PB9B bidirectional User I/O, Bank 2, differential complement (C) of the pair.
70 SLEEPN input Active-low sleep mode pin (C devices only; NC on E devices); high for normal operation, weak internal pull-up, external pull-up to VCC recommended when unused.
71 PB9D bidirectional User I/O, Bank 2, differential complement (C) of the pair.
72 PB9F bidirectional User I/O, Bank 2.
73 PR11D bidirectional User I/O, Bank 1, differential complement (C) of the pair.
74 PR11B bidirectional User I/O, Bank 1, differential complement (C) of the pair.
75 PR11C bidirectional User I/O, Bank 1, differential true (T) of the pair.
76 PR10D bidirectional User I/O, Bank 1, differential complement (C) of the pair.
77 PR11A bidirectional User I/O, Bank 1, differential true (T) of the pair.
78 PR10B bidirectional User I/O, Bank 1, differential complement (C) of the pair.
79 PR10C bidirectional User I/O, Bank 1, differential true (T) of the pair.
80 PR10A bidirectional User I/O, Bank 1, differential true (T) of the pair.
81 PR9D bidirectional User I/O, Bank 1.
82 VCCIO1 power_in Power supply pin for I/O Bank 1.
83 GNDIO1 power_in Ground for I/O Bank 1.
84 PR9A bidirectional User I/O, Bank 1.
85 PR8C bidirectional User I/O, Bank 1.
86 PR8A bidirectional User I/O, Bank 1.
87 PR7D bidirectional User I/O, Bank 1.
88 GND power_in Ground, dedicated pin; all grounds must be connected at board level.
89 PR7B bidirectional User I/O, Bank 1, differential complement (C) of the pair.
90 PR7A bidirectional User I/O, Bank 1, differential true (T) of the pair.
91 PR6D bidirectional User I/O, Bank 1, differential complement (C) of the pair.
92 PR6C bidirectional User I/O, Bank 1, differential true (T) of the pair.
93 VCC power_in Core logic power supply, dedicated pin.
94 PR5D bidirectional User I/O, Bank 1.
95 PR5B bidirectional User I/O, Bank 1.
96 PR4D bidirectional User I/O, Bank 1.
97 PR4B bidirectional User I/O, Bank 1, differential complement (C) of the pair.
98 VCCIO1 power_in Power supply pin for I/O Bank 1.
99 GNDIO1 power_in Ground for I/O Bank 1.
100 PR4A bidirectional User I/O, Bank 1, differential true (T) of the pair.
101 PR3D bidirectional User I/O, Bank 1, differential complement (C) of the pair.
102 PR3C bidirectional User I/O, Bank 1, differential true (T) of the pair.
103 PR3B bidirectional User I/O, Bank 1, differential complement (C) of the pair.
104 PR2D bidirectional User I/O, Bank 1, differential complement (C) of the pair.
105 PR3A bidirectional User I/O, Bank 1, differential true (T) of the pair.
106 PR2B bidirectional User I/O, Bank 1, differential complement (C) of the pair.
107 PR2C bidirectional User I/O, Bank 1, differential true (T) of the pair.
108 PR2A bidirectional User I/O, Bank 1, differential true (T) of the pair.
109 PT9F bidirectional User I/O, Bank 0, differential complement (C) of the pair.
110 PT9D bidirectional User I/O, Bank 0, differential complement (C) of the pair.
111 PT9E bidirectional User I/O, Bank 0, differential true (T) of the pair.
112 PT9B bidirectional User I/O, Bank 0, differential complement (C) of the pair.
113 PT9C bidirectional User I/O, Bank 0, differential true (T) of the pair.
114 PT9A bidirectional User I/O, Bank 0, differential true (T) of the pair.
115 PT8C bidirectional User I/O, Bank 0.
116 PT8B bidirectional User I/O, Bank 0, differential complement (C) of the pair.
117 VCCIO0 power_in Power supply pin for I/O Bank 0.
118 GNDIO0 power_in Ground for I/O Bank 0.
119 PT8A bidirectional User I/O, Bank 0, differential true (T) of the pair.
120 PT7E bidirectional User I/O, Bank 0.
121 PT7C bidirectional User I/O, Bank 0.
122 PT7A bidirectional User I/O, Bank 0.
123 GND power_in Ground, dedicated pin; all grounds must be connected at board level.
124 PT6B bidirectional User I/O, Bank 0, dual function primary clock input PCLK0_1 (single-ended), differential complement (C).
125 PT6A bidirectional User I/O, Bank 0, differential true (T) of the pair.
126 PT5C bidirectional User I/O, Bank 0.
127 PT5B bidirectional User I/O, Bank 0, dual function primary clock input PCLK0_0 (single-ended).
128 VCCAUX power_in Auxiliary power supply powering internal circuits including differential and referenced input buffers.
129 VCC power_in Core logic power supply, dedicated pin.
130 PT4D bidirectional User I/O, Bank 0.
131 PT4B bidirectional User I/O, Bank 0, differential complement (C) of the pair.
132 PT4A bidirectional User I/O, Bank 0, differential true (T) of the pair.
133 PT3F bidirectional User I/O, Bank 0.
134 PT3D bidirectional User I/O, Bank 0.
135 VCCIO0 power_in Power supply pin for I/O Bank 0.
136 GNDIO0 power_in Ground for I/O Bank 0.
137 PT3B bidirectional User I/O, Bank 0, differential complement (C) of the pair.
138 PT2F bidirectional User I/O, Bank 0, differential complement (C) of the pair.
139 PT3A bidirectional User I/O, Bank 0, differential true (T) of the pair.
140 PT2D bidirectional User I/O, Bank 0, differential complement (C) of the pair.
141 PT2E bidirectional User I/O, Bank 0, differential true (T) of the pair.
142 PT2B bidirectional User I/O, Bank 0, differential complement (C) of the pair.
143 PT2C bidirectional User I/O, Bank 0, differential true (T) of the pair.
144 PT2A bidirectional User I/O, Bank 0, differential true (T) of the pair.

Key specifications

Parameter Value
Manufacturer Lattice
Package TQFP-144(20x20)
Category Embedded Processors & Controllers
Pins 144

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Core Supply Voltage for 1.8V/2.5V/3.3V Devices VCC 1.71 3.465 V 27
Auxiliary Supply Voltage VCCAUX 3.135 3.465 V 27
I/O Driver Supply Voltage VCCIO 1.14 3.465 V 27
Junction Temperature Industrial Operation tJIND -40 100 °C 27
Junction Temperature, Flash Programming, Industrial tJFLASHIND -40 100 °C 27
Flash Programming Cycles per tRETENTION NPROGCYC 1000 Cycles 27
Flash Functional Programming Cycles NPROGCYC 10000 Cycles 27
Data Retention tRETENTION 10 Years at 125°C Junction Temperature 27
Supply Voltage VCC (C devices) VCC -0.5 3.75 V LCMXO C (1.8V/2.5V/3.3V) 27
Supply Voltage VCCAUX VCCAUX -0.5 3.75 V LCMXO C 27
Output Supply Voltage VCCIO VCCIO -0.5 3.75 V LCMXO C 27
I/O Tristate Voltage Applied -0.5 3.75 V LCMXO C 27
Dedicated Input Voltage Applied -0.5 4.25 V LCMXO C 27
Storage Temperature (ambient) -65 150 °C 27
Junction Temp. Tj 125 °C 27
Input or I/O leakage current (hot socketing) IDK -1000 1000 µA 0 ≤ VIN ≤ VIH (MAX) 28
Input or I/O Leakage IIL, IIH 10 µA 0 ≤ VIN ≤ (VCCIO - 0.2V) 28
Input or I/O Leakage IIL, IIH 40 µA (VCCIO - 0.2V) < VIN ≤ 3.6V 28
I/O Active Pull-up Current IPU -150 -30 µA 0 ≤ VIN ≤ 0.7 VCCIO 28
I/O Active Pull-down Current IPD 30 150 µA VIL (MAX) ≤ VIN ≤ VIH (MAX) 28
Bus Hold Low sustaining current IBHLS 30 µA VIN = VIL (MAX) 28
Bus Hold High sustaining current IBHHS -30 µA VIN = 0.7VCCIO 28
Bus Hold Low Overdrive current IBHLO 150 µA 0 ≤ VIN ≤ VIH (MAX) 28
Bus Hold High Overdrive current IBHHO -150 µA 0 ≤ VIN ≤ VIH (MAX) 28
I/O Capacitance C1 8 pf VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, VCC = Typ., VIO = 0 to VIH (MAX) 28
Dedicated Input Capacitance C2 8 pf VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, VCC = Typ., VIO = 0 to VIH (MAX) 28
Sleep Mode Core Power Supply Current LCMXO640C ICC 12 25 µA Sleep mode, TA = 25°C typ, nominal supplies 29
Sleep Mode Auxiliary Power Supply Current LCMXO640C ICCAUX 1 25 µA Sleep mode, TA = 25°C typ, nominal supplies 29
Sleep Mode Bank Power Supply Current ICCIO 2 30 µA Per Bank, All LCMXO C devices 29
Standby Core Power Supply Current LCMXO640C ICC 9 mA TJ = 25°C, nominal supplies, outputs tristated, frequency 0MHz, blank pattern 29
Standby Auxiliary Supply Current LCMXO640E/C ICCAUX 7 mA VCCAUX = 3.3V 29
Standby Bank Power Supply Current ICCIO 2 mA Per Bank, VCCIO = 2.5V, no pull-up/pull-down 29
Programming Core Supply Current LCMXO640C ICC 17 mA TJ = 25°C, nominal supplies, JTAG programming 25MHz 30
Programming Auxiliary Supply Current LCMXO640E/C ICCAUX 13 mA VCCAUX = 3.3V 30
Initialization Core Supply Current LCMXO640C ICC 11 mA TJ = 25°C, nominal supplies 30
Initialization Auxiliary Supply Current LCMXO640C/E ICCAUX 10 mA VCCAUX = 3.3V 30
Best Case tPD Through 1 LUT, LCMXO640, -3 tPD 4.9 ns Global clock without PLL, LVCMOS2.5V 12 mA 37
Best Case Clock to Output From PFU, LCMXO640, -3 tCO 5.7 ns Global clock without PLL 37
Clock to Data Setup To PFU, LCMXO640, -3 tSU 1.5 ns Global clock without PLL 37
Clock to Data Hold To PFU, LCMXO640, -3 tH -0.1 ns Global clock without PLL 37
Clock Frequency of I/O and PFU Register, LCMXO640, -3 fMAX_IO 500 MHz 37
Global Clock Skew Across Device, LCMXO640, -3 tSKEW_PRI 240 ps 37
LUT4 delay tLUT4_PFU 0.39 ns -3 38
Clock to Q delay, D-type register tCK2Q_PFU 0.56 ns -3 38
Input Buffer Delay tIN_PIO 1.06 ns -3 38
Output Buffer Delay tOUT_PIO 1.8 ns -3 38
SLEEPN Low to Power Down tPWRDN 400 ns 41
SLEEPN High to Power Up, LCMXO640 tPWRUP 600 µs 41
SLEEPN Pulse Width tWSLEEPN 400 ns 41
SLEEPN Pulse Rejection tWAWAKE 100 ns 41
Minimum VCC or VCCAUX to Device I/O Active, LCMXO640 tREFRESH 0.6 ms 41
TCK [BSCAN] clock frequency fMAX 25 MHz 41

CAD (KiCad official)

  • Symbol: LCMXO640C-3TN144I
  • Footprint: Package_QFP:TQFP-144_20x20mm_P0.5mm
  • 3D model: TQFP-144(20x20) (KiCad packages3D, STEP)
  • 3D model files: lcmxo640c-3tn144i-etched.step / lcmxo640c-3tn144i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lcmxo640c-3tn144i.step / lcmxo640c-3tn144i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Lattice datasheet (94 pp, sha256 ef1824c1615000b3, retrieved 2026-10-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF