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LCMXO256C-3TN100C

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Lattice Programmable Logic Device (CPLDs/FPGAs), TQFP-100(14x14). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

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LCMXO256C-3TN100C

Lattice · Programmable Logic Device (CPLDs/FPGAs) · TQFP-100(14x14)

LCMXO256C-3TN100C from Lattice, in a TQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PL2A bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
2 PL2B bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
3 PL3A bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
4 PL3B bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
5 PL3C bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
6 PL3D bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
7 PL4A bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
8 PL4B bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
9 PL5A bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
10 VCCIO1 power_in Bank 1 I/O supply voltage, supports 1.2V to 3.3V per configuration.
11 PL5B bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
12 GNDIO1 power_in Bank 1 I/O ground return.
13 PL5C bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
14 PL5D input Bank 1 programmable I/O, dual function with GSRN global reset (active low).
15 PL6A bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
16 PL6B input Bank 1 programmable I/O, dual function with TSALL global output tristate enable.
17 PL7A bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
18 PL7B bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
19 PL7C bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
20 PL7D bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
21 PL8A bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
22 PL8B bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
23 PL9A bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
24 VCCIO1 power_in Bank 1 I/O supply voltage, supports 1.2V to 3.3V per configuration.
25 GNDIO1 power_in Bank 1 I/O ground return.
26 TMS input Test Mode Select input pin for IEEE 1149.1 boundary scan test access port.
27 PL9B bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
28 TCK input Test Clock input pin for IEEE 1149.1 boundary scan test access port.
29 PB2A bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
30 PB2B bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
31 TDO output Test Data Output pin for IEEE 1149.1 boundary scan test access port.
32 PB2C bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
33 TDI input Test Data Input pin for IEEE 1149.1 boundary scan test access port.
34 PB2D bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
35 VCC power_in Core logic supply voltage, 1.8V to 3.3V per device variant.
36 PB3A input Bank 1 programmable I/O, dual function with PCLK1_1 primary clock input.
37 PB3B bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
38 PB3C input Bank 1 programmable I/O, dual function with PCLK1_0 primary clock input.
39 PB3D bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
40 GND power_in Ground return for core logic and I/O circuits.
41 VCCIO1 power_in Bank 1 I/O supply voltage, supports 1.2V to 3.3V per configuration.
42 GNDIO1 power_in Bank 1 I/O ground return.
43 PB4A bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
44 PB4B bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
45 PB4C bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
46 PB4D bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
47 PB5A bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
48 SLEEPN input Sleep Mode pin (active low); device enters sleep mode when held low for 400 ns, NC for E devices.
49 PB5C bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
50 PB5D bidirectional Bank 1 programmable I/O, part of differential pair true/complement.
51 PR9B bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
52 PR9A bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
53 PR8B bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
54 PR8A bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
55 PR7D bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
56 PR7C bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
57 PR7B bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
58 PR7A bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
59 PR6B bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
60 VCCIO0 power_in Bank 0 I/O supply voltage, supports 1.2V to 3.3V per configuration.
61 PR6A bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
62 GNDIO0 power_in Bank 0 I/O ground return.
63 PR5D bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
64 PR5C bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
65 PR5B bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
66 PR5A bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
67 PR4B bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
68 PR4A bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
69 PR3D bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
70 PR3C bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
71 PR3B bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
72 PR3A bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
73 PR2B bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
74 VCCIO0 power_in Bank 0 I/O supply voltage, supports 1.2V to 3.3V per configuration.
75 GNDIO0 power_in Bank 0 I/O ground return.
76 PR2A bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
77 PT5C bidirectional Bank 0 programmable I/O, top side of device.
78 PT5B bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
79 PT5A bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
80 PT4F bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
81 PT4E bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
82 PT4D bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
83 PT4C bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
84 GND power_in Ground return for core logic and I/O circuits.
85 PT4B input Bank 0 programmable I/O, dual function with PCLK0_1 primary clock input.
86 PT4A input Bank 0 programmable I/O, dual function with PCLK0_0 primary clock input.
87 PT3D bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
88 VCCAUX power_in Auxiliary supply voltage 3.135V to 3.465V, powers differential and referenced input buffers.
89 PT3C bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
90 VCC power_in Core logic supply voltage, 1.8V to 3.3V per device variant.
91 PT3B bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
92 VCCIO0 power_in Bank 0 I/O supply voltage, supports 1.2V to 3.3V per configuration.
93 GNDIO0 power_in Bank 0 I/O ground return.
94 PT3A bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
95 PT2F bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
96 PT2E bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
97 PT2D bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
98 PT2C bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
99 PT2B bidirectional Bank 0 programmable I/O, part of differential pair true/complement.
100 PT2A bidirectional Bank 0 programmable I/O, part of differential pair true/complement.

Key specifications

Parameter Value
Manufacturer Lattice
Package TQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: LCMXO256C-3TN100C
  • Footprint: Package_QFP:TQFP-100_14x14mm_P0.5mm
  • 3D model: TQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: lcmxo256c-3tn100c-etched.step / lcmxo256c-3tn100c-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lcmxo256c-3tn100c.step / lcmxo256c-3tn100c.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Lattice datasheet (94 pp, sha256 ef1824c1615000b3, retrieved 2026-09-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF