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LCMXO1200C-4TN144C

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Lattice Programmable Logic Device (CPLDs/FPGAs), TQFP-144(20x20). Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

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LCMXO1200C-4TN144C

Lattice · Programmable Logic Device (CPLDs/FPGAs) · TQFP-144(20x20)

LCMXO1200C-4TN144C from Lattice, in a TQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PL2A bidirectional User-programmable I/O in Bank 7 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
2 PL2B bidirectional User-programmable I/O in Bank 7 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
3 PL3A bidirectional User-programmable I/O in Bank 7 with true LVDS output support, configurable as input or output with internal pull-up.
4 PL3B bidirectional User-programmable I/O in Bank 7 with true LVDS output support, configurable as input or output with internal pull-up.
5 PL3C bidirectional User-programmable I/O in Bank 7 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
6 PL3D bidirectional User-programmable I/O in Bank 7 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
7 PL4A bidirectional User-programmable I/O in Bank 7 with true LVDS output support, configurable as input or output with internal pull-up.
8 PL4B bidirectional User-programmable I/O in Bank 7 with true LVDS output support, configurable as input or output with internal pull-up.
9 PL4C bidirectional User-programmable I/O in Bank 7 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
10 VCCIO7 power_in I/O buffer power supply for Bank 7; ranges 1.14V to 3.465V depending on I/O standard used.
11 GNDIO7 power_in Ground connection for I/O Bank 7; all grounds must be electrically connected at board level.
12 PL5C bidirectional User-programmable I/O in Bank 7 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
13 PL6A bidirectional User-programmable I/O in Bank 7 with true LVDS output support, configurable as input or output with internal pull-up.
14 PL6B bidirectional User-programmable I/O in Bank 7 dual-function with GSRN (Global RESET active-low) capability; can be configured for general I/O or global reset.
15 PL6D bidirectional User-programmable I/O in Bank 7 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
16 GND power_in Ground connection; all grounds must be electrically connected at board level.
17 PL7C bidirectional User-programmable I/O in Bank 7 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
18 PL7D bidirectional User-programmable I/O in Bank 7 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
19 PL10A bidirectional User-programmable I/O in Bank 6 with true LVDS output support, configurable as input or output with internal pull-up.
20 PL10B bidirectional User-programmable I/O in Bank 6 with true LVDS output support, configurable as input or output with internal pull-up.
21 VCC power_in Core logic power supply; voltage range 1.71V to 3.465V, must reach minimum before VCCAUX reaches 2.5V.
22 PL11A bidirectional User-programmable I/O in Bank 6 with true LVDS output support, configurable as input or output with internal pull-up.
23 PL11B bidirectional User-programmable I/O in Bank 6 with true LVDS output support, configurable as input or output with internal pull-up.
24 PL11C bidirectional User-programmable I/O in Bank 6 dual-function with TSALL (global output enable) capability; when TSALL is high all outputs are tri-stated.
25 PL12B bidirectional User-programmable I/O in Bank 6 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
26 VCCIO6 power_in I/O buffer power supply for Bank 6; ranges 1.14V to 3.465V depending on I/O standard used.
27 GNDIO6 power_in Ground connection for I/O Bank 6; all grounds must be electrically connected at board level.
28 PL13D bidirectional User-programmable I/O in Bank 6 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
29 PL14A bidirectional User-programmable I/O in Bank 6 dual-function with PLL feedback input LLM0_PLLT_FB_A capability and true LVDS output support.
30 PL14B bidirectional User-programmable I/O in Bank 6 dual-function with PLL feedback input LLM0_PLLC_FB_A capability and true LVDS output support.
31 PL14C bidirectional User-programmable I/O in Bank 6 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
32 PL14D bidirectional User-programmable I/O in Bank 6 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
33 PL15A bidirectional User-programmable I/O in Bank 6 dual-function with PLL reference input LLM0_PLLT_IN_A capability and true LVDS output support.
34 PL15B bidirectional User-programmable I/O in Bank 6 dual-function with PLL reference input LLM0_PLLC_IN_A capability and true LVDS output support.
35 PL16A bidirectional User-programmable I/O in Bank 6 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
36 PL16B bidirectional User-programmable I/O in Bank 6 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
37 GNDIO5 power_in Ground connection for I/O Bank 5; all grounds must be electrically connected at board level.
38 VCCIO5 power_in I/O buffer power supply for Bank 5; ranges 1.14V to 3.465V depending on I/O standard used.
39 TMS input Test Mode Select input pin used to control the IEEE 1149.1 JTAG state machine; operates at clock frequency ≤25 MHz.
40 PB2C bidirectional User-programmable I/O in Bank 5 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
41 PB2D bidirectional User-programmable I/O in Bank 5 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
42 TCK input Test Clock input pin used to clock the IEEE 1149.1 JTAG state machine; operates at clock frequency ≤25 MHz.
43 PB3A bidirectional User-programmable I/O in Bank 5 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
44 PB3B bidirectional User-programmable I/O in Bank 5 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
45 PB4A bidirectional User-programmable I/O in Bank 5 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
46 PB4B bidirectional User-programmable I/O in Bank 5 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
47 TDO output Test Data output pin used to shift data out of the device during IEEE 1149.1 JTAG boundary scan testing.
48 PB4D bidirectional User-programmable I/O in Bank 5 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
49 PB5A bidirectional User-programmable I/O in Bank 5 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
50 PB5B bidirectional User-programmable I/O in Bank 5 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
51 TDI input Test Data input pin used to load data into the device via IEEE 1149.1 JTAG state machine during testing and configuration.
52 VCC power_in Core logic power supply; voltage range 1.71V to 3.465V, must reach minimum before VCCAUX reaches 2.5V.
53 VCCAUX power_in Auxiliary power supply for differential/referenced input buffers and PLL circuitry; range 3.135V to 3.465V.
54 PB6F bidirectional User-programmable I/O in Bank 5 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
55 PB7B bidirectional User-programmable I/O in Bank 4 dual-function with PCLK4_1 primary clock input capability; can be configured as clock input or general I/O.
56 PB7C bidirectional User-programmable I/O in Bank 4 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
57 PB7D bidirectional User-programmable I/O in Bank 4 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
58 PB7F bidirectional User-programmable I/O in Bank 4 dual-function with PCLK4_0 primary clock input capability; can be configured as clock input or general I/O.
59 GND power_in Ground connection; all grounds must be electrically connected at board level.
60 PB9A bidirectional User-programmable I/O in Bank 4 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
61 PB9B bidirectional User-programmable I/O in Bank 4 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
62 PB9E bidirectional User-programmable I/O in Bank 4 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
63 VCCIO4 power_in I/O buffer power supply for Bank 4; ranges 1.14V to 3.465V depending on I/O standard used.
64 GNDIO4 power_in Ground connection for I/O Bank 4; all grounds must be electrically connected at board level.
65 PB10A bidirectional User-programmable I/O in Bank 4 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
66 PB10B bidirectional User-programmable I/O in Bank 4 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
67 PB10C bidirectional User-programmable I/O in Bank 4 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
68 PB10D bidirectional User-programmable I/O in Bank 4 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
69 PB10F bidirectional User-programmable I/O in Bank 4 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
70 SLEEPN input Active-low sleep mode control pin; holding low moves device to sleep mode reducing static current to <100 µA with logic non-operational.
71 PB11C bidirectional User-programmable I/O in Bank 4 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
72 PB11D bidirectional User-programmable I/O in Bank 4 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
73 PR16B bidirectional User-programmable I/O in Bank 3 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
74 PR16A bidirectional User-programmable I/O in Bank 3 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
75 PR15B bidirectional User-programmable I/O in Bank 3 with true LVDS output support, configurable as input or output with internal pull-up.
76 PR15A bidirectional User-programmable I/O in Bank 3 with true LVDS output support, configurable as input or output with internal pull-up.
77 PR14D bidirectional User-programmable I/O in Bank 3 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
78 PR14C bidirectional User-programmable I/O in Bank 3 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
79 PR14B bidirectional User-programmable I/O in Bank 3 with true LVDS output support, configurable as input or output with internal pull-up.
80 PR14A bidirectional User-programmable I/O in Bank 3 with true LVDS output support, configurable as input or output with internal pull-up.
81 PR13D bidirectional User-programmable I/O in Bank 3 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
82 VCCIO3 power_in I/O buffer power supply for Bank 3; ranges 1.14V to 3.465V depending on I/O standard used.
83 GNDIO3 power_in Ground connection for I/O Bank 3; all grounds must be electrically connected at board level.
84 PR12B bidirectional User-programmable I/O in Bank 3 with true LVDS output support, configurable as input or output with internal pull-up.
85 PR12A bidirectional User-programmable I/O in Bank 3 with true LVDS output support, configurable as input or output with internal pull-up.
86 PR11B bidirectional User-programmable I/O in Bank 3 with true LVDS output support, configurable as input or output with internal pull-up.
87 PR11A bidirectional User-programmable I/O in Bank 3 with true LVDS output support, configurable as input or output with internal pull-up.
88 GND power_in Ground connection; all grounds must be electrically connected at board level.
89 PR10B bidirectional User-programmable I/O in Bank 3 with true LVDS output support, configurable as input or output with internal pull-up.
90 PR10A bidirectional User-programmable I/O in Bank 3 with true LVDS output support, configurable as input or output with internal pull-up.
91 PR8B bidirectional User-programmable I/O in Bank 2 with true LVDS output support, configurable as input or output with internal pull-up.
92 PR8A bidirectional User-programmable I/O in Bank 2 with true LVDS output support, configurable as input or output with internal pull-up.
93 VCC power_in Core logic power supply; voltage range 1.71V to 3.465V, must reach minimum before VCCAUX reaches 2.5V.
94 PR6B bidirectional User-programmable I/O in Bank 2 with true LVDS output support, configurable as input or output with internal pull-up.
95 PR6A bidirectional User-programmable I/O in Bank 2 with true LVDS output support, configurable as input or output with internal pull-up.
96 PR5B bidirectional User-programmable I/O in Bank 2 with true LVDS output support, configurable as input or output with internal pull-up.
97 PR5A bidirectional User-programmable I/O in Bank 2 with true LVDS output support, configurable as input or output with internal pull-up.
98 VCCIO2 power_in I/O buffer power supply for Bank 2; ranges 1.14V to 3.465V depending on I/O standard used.
99 GNDIO2 power_in Ground connection for I/O Bank 2; all grounds must be electrically connected at board level.
100 PR4C bidirectional User-programmable I/O in Bank 2 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
101 PR4B bidirectional User-programmable I/O in Bank 2 with true LVDS output support, configurable as input or output with internal pull-up.
102 PR4A bidirectional User-programmable I/O in Bank 2 with true LVDS output support, configurable as input or output with internal pull-up.
103 PR3D bidirectional User-programmable I/O in Bank 2 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
104 PR3C bidirectional User-programmable I/O in Bank 2 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
105 PR3B bidirectional User-programmable I/O in Bank 2 with true LVDS output support, configurable as input or output with internal pull-up.
106 PR3A bidirectional User-programmable I/O in Bank 2 with true LVDS output support, configurable as input or output with internal pull-up.
107 PR2B bidirectional User-programmable I/O in Bank 2 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
108 PR2A bidirectional User-programmable I/O in Bank 2 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
109 PT11D bidirectional User-programmable I/O in Bank 1 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
110 PT11C bidirectional User-programmable I/O in Bank 1 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
111 PT11B bidirectional User-programmable I/O in Bank 1 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
112 PT11A bidirectional User-programmable I/O in Bank 1 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
113 PT10F bidirectional User-programmable I/O in Bank 1 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
114 PT10E bidirectional User-programmable I/O in Bank 1 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
115 PT10D bidirectional User-programmable I/O in Bank 1 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
116 PT10C bidirectional User-programmable I/O in Bank 1 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
117 VCCIO1 power_in I/O buffer power supply for Bank 1; ranges 1.14V to 3.465V depending on I/O standard used.
118 GNDIO1 power_in Ground connection for I/O Bank 1; all grounds must be electrically connected at board level.
119 PT9F bidirectional User-programmable I/O in Bank 1 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
120 PT9E bidirectional User-programmable I/O in Bank 1 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
121 PT9B bidirectional User-programmable I/O in Bank 1 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
122 PT9A bidirectional User-programmable I/O in Bank 1 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
123 GND power_in Ground connection; all grounds must be electrically connected at board level.
124 PT7D bidirectional User-programmable I/O in Bank 1 dual-function with PCLK1_1 primary clock input capability; can be configured as clock input or general I/O.
125 PT7B bidirectional User-programmable I/O in Bank 1 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
126 PT7A bidirectional User-programmable I/O in Bank 1 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
127 PT6F bidirectional User-programmable I/O in Bank 0 dual-function with PCLK1_0 primary clock input capability; can be configured as clock input or general I/O.
128 VCCAUX power_in Auxiliary power supply for differential/referenced input buffers and PLL circuitry; range 3.135V to 3.465V.
129 VCC power_in Core logic power supply; voltage range 1.71V to 3.465V, must reach minimum before VCCAUX reaches 2.5V.
130 PT5D bidirectional User-programmable I/O in Bank 0 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
131 PT5C bidirectional User-programmable I/O in Bank 0 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
132 PT5B bidirectional User-programmable I/O in Bank 0 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
133 PT5A bidirectional User-programmable I/O in Bank 0 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
134 PT4B bidirectional User-programmable I/O in Bank 0 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
135 VCCIO0 power_in I/O buffer power supply for Bank 0; ranges 1.14V to 3.465V depending on I/O standard used.
136 GNDIO0 power_in Ground connection for I/O Bank 0; all grounds must be electrically connected at board level.
137 PT3D bidirectional User-programmable I/O in Bank 0 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
138 PT3C bidirectional User-programmable I/O in Bank 0 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
139 PT3B bidirectional User-programmable I/O in Bank 0 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
140 PT3A bidirectional User-programmable I/O in Bank 0 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
141 PT2D bidirectional User-programmable I/O in Bank 0 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
142 PT2C bidirectional User-programmable I/O in Bank 0 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
143 PT2B bidirectional User-programmable I/O in Bank 0 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.
144 PT2A bidirectional User-programmable I/O in Bank 0 supporting multiple I/O standards with programmable tri-state, pull-up, and drive strength.

Key specifications

Parameter Value
Manufacturer Lattice
Package TQFP-144(20x20)
Category Embedded Processors & Controllers
Pins 144

CAD (KiCad official)

  • Symbol: LCMXO1200C-4TN144C
  • Footprint: Package_QFP:TQFP-144_20x20mm_P0.5mm
  • 3D model: TQFP-144(20x20) (KiCad packages3D, STEP)
  • 3D model files: lcmxo1200c-4tn144c-etched.step / lcmxo1200c-4tn144c-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lcmxo1200c-4tn144c.step / lcmxo1200c-4tn144c.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Lattice datasheet (94 pp, sha256 ef1824c1615000b3, retrieved 2026-09-29, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF