component
LCMXO1200C-4TN144C
Public Made by Adomby adom
Lattice Programmable Logic Device (CPLDs/FPGAs), TQFP-144(20x20). Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.
← Commit history
page.json+7−4@@ -281,7 +281,7 @@ "number": "39", "name": "TMS", "type": "input",- "description": "Test Mode Select input pin used to control the IEEE 1149.1 JTAG state machine; operates at clock frequency \u226425 MHz."+ "description": "Test Mode Select input pin used to control the IEEE 1149.1 JTAG state machine; operates at clock frequency ≤25 MHz." }, { "number": "40",@@ -299,7 +299,7 @@ "number": "42", "name": "TCK", "type": "input",- "description": "Test Clock input pin used to clock the IEEE 1149.1 JTAG state machine; operates at clock frequency \u226425 MHz."+ "description": "Test Clock input pin used to clock the IEEE 1149.1 JTAG state machine; operates at clock frequency ≤25 MHz." }, { "number": "43",@@ -467,7 +467,7 @@ "number": "70", "name": "SLEEPN", "type": "input",- "description": "Active-low sleep mode control pin; holding low moves device to sleep mode reducing static current to <100 \u00b5A with logic non-operational."+ "description": "Active-low sleep mode control pin; holding low moves device to sleep mode reducing static current to <100 µA with logic non-operational." }, { "number": "71",@@ -976,5 +976,8 @@ "docs/lcmxo1200c-4tn144c-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ]+ ],+ "visibility": {+ "public": true+ } }