component
LC03-6R2G
Public Made by Adomby adom
onsemi ESD Protection Devices, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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LC03-6R2G
onsemi · ESD Protection Devices · SOIC-8
LC03-6R2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I/O1 | passive | Line 1 data-line protection terminal, tied internally to pin 8, with 16 pF typ (25 pF max) capacitance to ground at 0 V, 1 MHz. |
| 2 | GND | power_in | Ground return terminal connected to ground, tied internally to pins 3, 6 and 7, and kept to short PCB traces and ground planes to minimize parasitic inductance. |
| 3 | GND | power_in | Ground return terminal connected to ground, tied internally to pins 2, 6 and 7, and kept to short PCB traces and ground planes to minimize parasitic inductance. |
| 4 | I/O2 | passive | Line 2 data-line protection terminal, tied internally to pin 5, with 16 pF typ (25 pF max) capacitance to ground at 0 V, 1 MHz. |
| 5 | I/O2 | passive | Line 2 data-line protection terminal, tied internally to pin 4, with 16 pF typ (25 pF max) capacitance to ground at 0 V, 1 MHz. |
| 6 | GND | power_in | Ground return terminal connected to ground, tied internally to pins 2, 3 and 7, and kept to short PCB traces and ground planes to minimize parasitic inductance. |
| 7 | GND | power_in | Ground return terminal connected to ground, tied internally to pins 2, 3 and 6, and kept to short PCB traces and ground planes to minimize parasitic inductance. |
| 8 | I/O1 | passive | Line 1 data-line protection terminal, tied internally to pin 1, with 16 pF typ (25 pF max) capacitance to ground at 0 V, 1 MHz. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Circuit Protection |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Reverse Breakdown Voltage | VBR | 6.8 | V | @ It = 1.0 mA | 2 | ||
| Reverse Leakage Current | IR | 20 | µA | @ VRWM = 5.0 V | 2 | ||
| Maximum Clamping Voltage | VC | 15 | V | @ IPP = 50 A, 8 x 20 µs | 2 | ||
| Maximum Clamping Voltage | VC | 20 | V | @ IPP = 100 A, 8 x 20 µs | 2 | ||
| Between I/O Pins and Ground Capacitance | 16 | 25 | pF | @ VR = 0 V, 1.0 MHz | 2 | ||
| Between I/O Pins Capacitance | 8 | 12 | pF | @ VR = 0 V, 1.0 MHz | 2 | ||
| Peak Power Dissipation | Ppk | 2000 | W | 8 x 20 µs @ TA = 25°C (Note 1) | 1 | ||
| Peak Pulse Current (8 x 20 µs Waveform) | IPP | 100 | A | 8 x 20 µs waveform | 1 | ||
| Junction and Storage Temperature Range | TJ, Tstg | -55 | 150 | °C | 1 | ||
| Lead Solder Temperature | TL | 260 | °C | Maximum 10 Seconds Duration | 1 |
CAD (KiCad official)
- Symbol:
LC03-6R2G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
lc03-6r2g-etched.step/lc03-6r2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lc03-6r2g.step/lc03-6r2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (6 pp, sha256
a2bb268244dd527d, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).