component

LBSS139LT1G

Public Made by Adom

by adom

LRC MOSFETs, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs Publish 0.1.0 · Ray 1mo ago
viewers lbss139lt1g: viewers · Ray 1mo ago
lbss139lt1g-etched.glb lbss139lt1g: factory component page (tier=lcsc) · Ray 1mo ago
lbss139lt1g-etched.step lbss139lt1g: factory component page (tier=lcsc) · Ray 1mo ago
lbss139lt1g-hero.glb lbss139lt1g: hero GLB from the etched model (keeps the MPN mark) · Ray 1mo ago
lbss139lt1g-hero.overlay.json Publish 0.1.0 · Ray 1mo ago
lbss139lt1g.glb Publish 0.1.0 · Ray 1mo ago
lbss139lt1g.kicad_mod Publish 0.1.0 · Ray 1mo ago
lbss139lt1g.kicad_sym Publish 0.1.0 · Ray 1mo ago
lbss139lt1g.lbr Publish 0.1.0 · Ray 1mo ago
lbss139lt1g.step Publish 0.1.0 · Ray 1mo ago
package.json Publish 0.1.0 · Ray 1mo ago
page.json lbss139lt1g: specified limits as data (metadata.characteristics, 16 rows from the datasheet) · Ray 23d ago
README.md lbss139lt1g: specified limits as data (metadata.characteristics, 16 rows from the datasheet) · Ray 23d ago

LBSS139LT1G

LRC · MOSFETs · SOT-23

LBSS139LT1G from LRC, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Gate input Gate terminal with ESD protection to 1500V; gate-to-source voltage limited to ±20 Vdc continuous, with threshold VGS(th) of 0.5V to 1.5V.
2 Source passive Source terminal of the N-channel MOSFET; continuous drain current is 200 mAdc (800 mAdc pulsed) at TA = 25°C.
3 Drain passive Drain terminal of the N-channel MOSFET; drain-source voltage is limited to 50 Vdc.

Key specifications

Parameter Value
Manufacturer LRC
Package SOT-23
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain–Source Breakdown Voltage VBRDSS 50 Vdc VGS = 0, ID = 250 μAdc 2
Gate Threshold Voltage VGS(th) 0.5 1.5 Vdc VDS = VGS, ID = 1.0 mAdc 2
Zero Gate Voltage Drain Current IDSS 0.1 μAdc VGS = 0, VDS = 25 Vdc 2
Zero Gate Voltage Drain Current IDSS 0.5 μAdc VGS = 0, VDS = 50 Vdc 2
Gate–Body Leakage Current, Forward IGSSF 10 μAdc VGS = 20 Vdc 2
Gate–Body Leakage Current, Reverse IGSSR -10 μAdc VGS = -20 Vdc 2
Static Drain–Source On–State Resistance RDS(on) 10 Ohms VGS = 2.75 Vdc, ID < 200 mAdc, TA = –40°C to +85°C 2
Forward Transconductance gfs 100 mS VDS = 25 Vdc, ID = 200 mAdc, f = 1.0 kHz 2
Gate–Source Voltage – Continuous VGS -20 20 Vdc Continuous 1
Drain–Source Voltage VDSS 50 Vdc 1
Drain Current – Continuous ID 200 mAdc TA = 25°C 1
Drain Current – Pulsed IDM 800 mAdc tp ≤ 10 μs 1
Total Device Dissipation, FR-4 Board PD 225 mW FR-4 board (Note 1), TA = 25°C 1
Thermal Resistance, Junction–to–Ambient RΘJA 556 °C/W FR-4 board (Note 1) 1
Junction and Storage Temperature TJ,Tstg -55 150 °C 1
Maximum Lead Temperature for Soldering Purposes TL 260 °C 10 seconds 1

CAD (KiCad official)

  • Symbol: LBSS139LT1G
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: lbss139lt1g-etched.step / lbss139lt1g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lbss139lt1g.step / lbss139lt1g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LRC datasheet (7 pp, sha256 b3d99d6c4802318f, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF