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LAN9514-JZX

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Microchip Tech USB ICs, QFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icslan9514-jzxfactory-2.0.0extractor-text

Verified LAN9514-JZX

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 65 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: LAN9514-JZX · QFN-64-EP(9x9) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 54-page datasheet
  • ✓distributor: lcsc C514074, digikey 638-1087-ND, mouser 886-LAN9514-JZX
  • ✓family: QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-lgql_8z4/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.47)
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ lan9514-jzx.kicad_sym✓ lan9514-jzx.kicad_mod✓ lan9514-jzx.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 4d ago
viewers lan9514-jzx: viewers · Ray 4d ago
lan9514-jzx-etched.glb Publish 0.1.0 · Ray 4d ago
lan9514-jzx-etched.step lan9514-jzx: factory component page (tier=mfr) · Ray 4d ago
lan9514-jzx-hero.glb lan9514-jzx: hero GLB from the etched model (keeps the MPN mark) · Ray 4d ago
lan9514-jzx-hero.overlay.json Publish 0.1.0 · Ray 4d ago
lan9514-jzx.glb Publish 0.1.0 · Ray 4d ago
lan9514-jzx.kicad_mod Publish 0.1.0 · Ray 4d ago
lan9514-jzx.kicad_sym Publish 0.1.0 · Ray 4d ago
lan9514-jzx.lbr Publish 0.1.0 · Ray 4d ago
lan9514-jzx.step Publish 0.1.0 · Ray 4d ago
package.json Publish 0.1.0 · Ray 4d ago
page.json Set visibility: public · Ray 4d ago
README.md Publish 0.1.0 · Ray 4d ago
verification.json Verified: Published by the parts factory: tier mfr, 65 pins · Ray 4d ago

LAN9514-JZX

Microchip Tech · USB ICs · QFN-64-EP(9x9)

LAN9514-JZX from Microchip Tech, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 USBDM2 bidirectional Downstream USB peripheral 2 DMINUS signal.
2 USBDP2 bidirectional Downstream USB peripheral 2 DPLUS signal.
3 USBDM3 bidirectional Downstream USB peripheral 3 DMINUS signal.
4 USBDP3 bidirectional Downstream USB peripheral 3 DPLUS signal.
5 VDD33A power_in +3.3V analog power supply; see the reference schematics for connection information.
6 USBDM4 bidirectional Downstream USB peripheral 4 DMINUS signal.
7 USBDP4 bidirectional Downstream USB peripheral 4 DPLUS signal.
8 USBDM5 bidirectional Downstream USB peripheral 5 DMINUS signal.
9 USBDP5 bidirectional Downstream USB peripheral 5 DPLUS signal.
10 VDD33A power_in +3.3V analog power supply; see the reference schematics for connection information.
11 VBUS_DET input 5V-tolerant Schmitt input detecting upstream bus power to decide when to assert the USBDP0 pull-up; must be tied to VDD33IO for bus-powered hubs.
12 nRESET input Active-low Schmitt-triggered system reset input from external hardware; tie high if unused.
13 TEST1 unconnected Factory test pin that must always be left unconnected.
14 PRTCTL2 bidirectional USB port power control 2: output enables power to downstream port 2, input samples the external current monitor (low indicates overcurrent); IS/OD12 with internal pull-up.
15 VDD18CORE power_out +1.8V output of the internal core voltage regulator; all VDD18CORE pins must be tied together.
16 PRTCTL3 bidirectional USB port power control 3: output enables power to downstream port 3, input samples the external current monitor (low indicates overcurrent); IS/OD12 with internal pull-up.
17 PRTCTL4 bidirectional USB port power control 4: output enables power to downstream port 4, input samples the external current monitor (low indicates overcurrent); IS/OD12 with internal pull-up.
18 PRTCTL5 bidirectional USB port power control 5: output enables power to downstream port 5, input samples the external current monitor (low indicates overcurrent); IS/OD12 with internal pull-up.
19 VDD33IO power_in +3.3V power supply for I/O pins.
20 nFDX_LED/GPIO0 bidirectional Full-duplex LED output driven low when the link is full-duplex, or GPIO0 programmable as push-pull output, open-drain output or Schmitt input (OD12/O12/IS, internal pull-up).
21 nLNKA_LED/GPIO1 bidirectional Link/activity LED output driven low on valid link and pulsed high for 80 ms on TX/RX activity, or GPIO1 programmable as push-pull, open-drain or Schmitt input (internal pull-up).
22 nSPD_LED/GPIO2 bidirectional Speed LED output driven low at 100 Mbps or during auto-negotiation and high at 10 Mbps, or GPIO2 programmable as push-pull, open-drain or Schmitt input (internal pull-up).
23 EECLK output Drives the clock of the external EEPROM (O8).
24 EECS output Drives the chip select of the external EEPROM (O8).
25 EEDO output Drives the EEDI input of the external EEPROM (O8).
26 EEDI input EEPROM data input driven by the EEDO output of the external EEPROM, Schmitt input with internal pull-down.
27 VDD33IO power_in +3.3V power supply for I/O pins.
28 nTRST input Active-low JTAG test port reset input; tie high if not used.
29 TMS input JTAG test mode select input.
30 TDI input JTAG test data input.
31 TDO output JTAG test data output (O12).
32 TCK input JTAG test clock input; should be tied high through a 10 kOhm resistor.
33 VDD33IO power_in +3.3V power supply for I/O pins.
34 TEST2 input Factory test pin that must always be connected to VSS for proper operation.
35 GPIO3 bidirectional General purpose I/O 3 programmable as push-pull output, open-drain output or Schmitt input (IS/O8/OD8, internal pull-up).
36 GPIO4 bidirectional General purpose I/O 4 programmable as push-pull output, open-drain output or Schmitt input (IS/O8/OD8, internal pull-up).
37 GPIO5 bidirectional General purpose I/O 5 programmable as push-pull output, open-drain output or Schmitt input (IS/O8/OD8, internal pull-up).
38 VDD18CORE power_out +1.8V output of the internal core voltage regulator; all VDD18CORE pins must be tied together.
39 VDD33IO power_in +3.3V power supply for I/O pins.
40 TEST3 input Factory test pin that must always be connected to VDD33IO for proper operation.
41 AUTOMDIX_EN input Sets default Auto-MDIX setting: 0 = disabled, 1 = enabled.
42 GPIO6 bidirectional General purpose I/O 6 programmable as push-pull output, open-drain output or Schmitt input (IS/O8/OD8, internal pull-up).
43 GPIO7 bidirectional General purpose I/O 7 programmable as push-pull output, open-drain output or Schmitt input (IS/O8/OD8, internal pull-up).
44 CLK24_EN input Enables generation of the 24 MHz clock on the CLK24_OUT pin.
45 CLK24_OUT output Outputs a 24 MHz clock usable as a reference clock for a partner hub.
46 VDD33IO power_in +3.3V power supply for I/O pins.
47 TEST4 unconnected Factory test pin that must always be left unconnected.
48 VDD18ETHPLL power_in Ethernet PLL +1.8V power supply; see the reference schematics for connection information.
49 VDD33A power_in +3.3V analog power supply; see the reference schematics for connection information.
50 EXRES passive External PHY bias resistor pin for internal bias circuits; connect to an external 12.4K 1.0% resistor to ground.
51 VDD33A power_in +3.3V analog power supply; see the reference schematics for connection information.
52 RXP bidirectional Positive input of the Ethernet receiver, which may be swapped internally with the transmit outputs when Auto-MDIX is enabled.
53 RXN bidirectional Negative input of the Ethernet receiver, which may be swapped internally with the transmit outputs when Auto-MDIX is enabled.
54 VDD33A power_in +3.3V analog power supply; see the reference schematics for connection information.
55 TXP bidirectional Positive output of the Ethernet transmitter, which may be swapped internally with the receive inputs when Auto-MDIX is enabled.
56 TXN bidirectional Negative output of the Ethernet transmitter, which may be swapped internally with the receive inputs when Auto-MDIX is enabled.
57 VDD33A power_in +3.3V analog power supply; see the reference schematics for connection information.
58 USBDM0 bidirectional Upstream USB DMINUS signal.
59 USBDP0 bidirectional Upstream USB DPLUS signal.
60 XO output External 25 MHz crystal output; leave unconnected when XI is driven by a single-ended clock oscillator.
61 XI input External 25 MHz crystal input, which can also be driven by a single-ended clock oscillator.
62 VDD18USBPLL power_in USB PLL +1.8V power supply; see the reference schematics for connection information.
63 USBRBIAS passive Sets HS transmit current level and on-chip termination impedance; connect to an external 12K 1.0% resistor to ground.
64 VDD33A power_in +3.3V analog power supply; see the reference schematics for connection information.
65 VSS power_in Exposed pad on package bottom is ground and must be connected to VSS.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-64-EP(9x9)
Category Interface ICs
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (VDD33IO, VDD33A) 0 3.6 V 38
Positive voltage on signal pins, with respect to ground 6 V with respect to ground (Note 4-2) 38
Negative voltage on signal pins, with respect to ground -0.5 V with respect to ground (Note 4-3) 38
Positive voltage on XI, with respect to ground 4.6 V with respect to ground 38
Positive voltage on XO, with respect to ground 2.5 V with respect to ground 38
Storage Temperature -55 150 °C 38
HBM ESD Performance -8 8 kV per JESD 22-A114-E 38
Contact Discharge ESD Performance -8 8 kV per IEC61000-4-2 (Note 4-5) 38
Air-Gap Discharge ESD Performance -15 15 kV per IEC61000-4-2 (Note 4-5) 38
Latch-up Performance -200 200 mA per EIA/JESD 78 38
Supply Voltage (VDD33A, VDD33BIAS, VDD33IO) 3 3.3 3.6 V +3.3V +/- 300 mV 38
Ambient Operating Temperature in Still Air TA 0 70 °C Commercial version (Note 4-4) 38
IS type input Low Input Level VILI -0.3 V 41
IS type input High Input Level VIHI 3.6 V 41
IS type input Negative-Going Threshold VILT 1.01 1.18 1.35 V Schmitt trigger 41
IS type input Positive-Going Threshold VIHT 1.39 1.6 1.8 V Schmitt trigger 41
IS type input Schmitt Trigger Hysteresis (VIHT - VILT) VHYS 345 420 485 mV Schmitt trigger 41
IS type input Input Leakage IIH -10 10 μA VIN = VSS or VDD33IO; Note 4-6 41
IS_5V type input Low Input Level VILI -0.3 V 41
IS_5V type input High Input Level VIHI 5.5 V 41
IS_5V type input Negative-Going Threshold VILT 1.01 1.18 1.35 V Schmitt trigger 41
IS_5V type input Positive-Going Threshold VIHT 1.39 1.6 1.8 V Schmitt trigger 41
IS_5V type input Schmitt Trigger Hysteresis (VIHT - VILT) VHYS 345 420 485 mV Schmitt trigger 41
IS_5V type input Input Leakage IIH -10 10 μA VIN = VSS or VDD33IO; Note 4-6 41
IS_5V type input Input Leakage (5.5V) IIH 120 μA VIN = 5.5V; Note 4-6, Note 4-7 41
O8 Type Buffer Low Output Level VOL 0.4 V IOL = 8mA 41
OD8 Type Buffer Low Output Level VOL 0.4 V IOL = 8mA 41
O12 Type Buffer Low Output Level VOL 0.4 V IOL = 12mA 41
OD12 Type Buffer Low Output Level VOL 0.4 V IOL = 12mA 41
ICLK Type Buffer (XI Input) Low Input Level VILI -0.3 0.5 V Note 4-8 42
ICLK Type Buffer (XI Input) High Input Level VIHI 1.4 3.6 V Note 4-8 42
100BASE-TX Peak Differential Output Voltage High VPPH 950 1050 mVpk Note 4-9 42
100BASE-TX Peak Differential Output Voltage Low VPPL -950 -1050 mVpk Note 4-9 42
100BASE-TX Signal Amplitude Symmetry VSS 98 102 % Note 4-9 42
100BASE-TX Signal Rise and Fall Time TRF 3 5 nS Note 4-9 42
100BASE-TX Rise and Fall Symmetry TRFS 0.5 nS Note 4-9 42
100BASE-TX Duty Cycle Distortion DCD 35 50 65 % Note 4-10 42
100BASE-TX Overshoot and Undershoot VOS 5 % 42
100BASE-TX Jitter 1.4 nS Note 4-11 42
10BASE-T Transmitter Peak Differential Output Voltage VOUT 2.2 2.5 2.8 V Note 4-12 42
10BASE-T Receiver Differential Squelch Threshold VDS 300 420 585 mV 42
TCK clock period ttckp 66.67 ns 45
TDI, TMS setup to TCK rising edge tsu 10 ns 45
TDI, TMS hold from TCK rising edge th 10 ns 45
TDO output valid from TCK falling edge tdov 16 ns 45
TDO output hold from TCK falling edge tdoh 0 ns 45
Frequency Tolerance @ 25°C Ftol -50 50 PPM @ 25°C; Note 4-13 45
Frequency Stability Over Temp Ftemp -50 50 PPM Note 4-13 45
Total Allowable PPM Budget -50 50 PPM Note 4-15 45
Drive Level PW 300 uW 45
Equivalent Series Resistance R1 50 Ω 45
nRESET input assertion time 1 μS minimum assertion period 43
Input clock duty cycle (single-ended clock oscillator on XI) 40 50 60 % single-ended clock oscillator on XI 45
Nominal single-ended clock signal on XI 0 3.3 V nominal clock signal driven on XI, XO unconnected 45

CAD (KiCad official)

  • Symbol: LAN9514-JZX
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: lan9514-jzx-etched.step / lan9514-jzx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lan9514-jzx.step / lan9514-jzx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (54 pp, sha256 5dc719b1a8f27350, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF