Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗

Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗

Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗

Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗

Loads on click. Unloads only if this page sits in the background.

Download PDF

Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

LAN9512I-JZX

Microchip Tech · Ethernet Controllers · QFN-64-EP(9x9)

LAN9512I-JZX from Microchip Tech, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	USBDM2	bidirectional	Downstream USB peripheral 2 DMINUS differential signal.
2	USBDP2	bidirectional	Downstream USB peripheral 2 DPLUS differential signal.
3	USBDM3	bidirectional	Downstream USB peripheral 3 DMINUS differential signal.
4	USBDP3	bidirectional	Downstream USB peripheral 3 DPLUS differential signal.
5	VDD33A	power_in	+3.3V analog power supply.
6	NC	unconnected	No connect pin; must be left floating for normal device operation.
7	NC	unconnected	No connect pin; must be left floating for normal device operation.
8	NC	unconnected	No connect pin; must be left floating for normal device operation.
9	NC	unconnected	No connect pin; must be left floating for normal device operation.
10	VDD33A	power_in	+3.3V analog power supply.
11	VBUS_DET	input	Upstream VBUS power detect with 5V tolerant Schmitt input; must be tied to VDD33IO for bus-powered hubs.
12	nRESET	input	Active low system reset input; allows external hardware to reset the device.
13	TEST1	unconnected	Factory test pin; must be left unconnected for proper operation.
14	PRTCTL2	tri_state	USB port power control 2 with open-drain output and internal pull-up; controls power to downstream USB peripheral 2.
15	VDD18CORE	power_in	+1.8V digital core power supply output from internal regulator.
16	PRTCTL3	tri_state	USB port power control 3 with open-drain output and internal pull-up; controls power to downstream USB peripheral 3.
17	NC	unconnected	No connect pin; must be left floating for normal device operation.
18	NC	unconnected	No connect pin; must be left floating for normal device operation.
19	VDD33IO	power_in	+3.3V I/O power supply.
20	nFDX_LED/GPIO0	tri_state	Ethernet full-duplex indicator LED and general purpose I/O 0; open-drain output driven low when operating in full-duplex mode.
21	nLNKA_LED/GPIO1	tri_state	Ethernet link activity indicator LED and general purpose I/O 1; open-drain output pulsed to indicate transmit/receive activity.
22	nSPD_LED/GPIO2	tri_state	Ethernet speed indicator LED and general purpose I/O 2; open-drain output driven low at 100 Mbps or during auto-negotiation.
23	EECLK	output	EEPROM clock output with 8 mA sink/source capability; drives the external EEPROM clock.
24	EECS	output	EEPROM chip select output with 8 mA sink/source capability; drives the external EEPROM chip select.
25	EEDO	output	EEPROM data output with 8 mA sink/source capability; drives the EEDI input of the external EEPROM.
26	EEDI	input	EEPROM data input with internal pull-down; receives data from EEDO output of external EEPROM.
27	VDD33IO	power_in	+3.3V I/O power supply.
28	nTRST	input	JTAG test port reset (active low) with internal pull-up; must be tied high if not used.
29	TMS	input	JTAG test mode select with Schmitt trigger.
30	TDI	input	JTAG test data input with Schmitt trigger.
31	TDO	output	JTAG test data output with 12 mA sink/source capability.
32	TCK	input	JTAG test clock with Schmitt trigger; should be tied high through 10 kΩ resistor if not used.
33	VDD33IO	power_in	+3.3V I/O power supply.
34	TEST2	power_in	Factory test pin; must be connected to VSS for proper operation.
35	GPIO3	tri_state	General purpose I/O 3 with 8 mA sink/source and internal pull-up; programmable as push-pull output, open-drain output, or Schmitt input.
36	GPIO4	tri_state	General purpose I/O 4 with 8 mA sink/source and internal pull-up; programmable as push-pull output, open-drain output, or Schmitt input.
37	GPIO5	tri_state	General purpose I/O 5 with 8 mA sink/source and internal pull-up; programmable as push-pull output, open-drain output, or Schmitt input.
38	VDD18CORE	power_in	+1.8V digital core power supply output from internal regulator.
39	VDD33IO	power_in	+3.3V I/O power supply.
40	TEST3	power_in	Factory test pin; must be connected to VDD33IO for proper operation.
41	AUTOMDIX_EN	input	Auto-MDIX enable with Schmitt trigger; high enables Auto-MDIX, low disables it.
42	GPIO6	tri_state	General purpose I/O 6 with 8 mA sink/source and internal pull-up; programmable as push-pull output, open-drain output, or Schmitt input.
43	GPIO7	tri_state	General purpose I/O 7 with 8 mA sink/source and internal pull-up; programmable as push-pull output, open-drain output, or Schmitt input.
44	CLK24_EN	input	24 MHz clock enable with Schmitt trigger input.
45	CLK24_OUT	output	24 MHz clock output with 8 mA sink/source capability; provides reference clock for partner hub.
46	VDD33IO	power_in	+3.3V I/O power supply.
47	TEST4	unconnected	Factory test pin; must be left unconnected for proper operation.
48	VDD18ETHPLL	power_in	Ethernet PLL +1.8V power supply.
49	VDD33A	power_in	+3.3V analog power supply.
50	EXRES	input	External Ethernet PHY bias resistor connection; connect to external 12.4K 1.0% resistor to ground for internal bias circuits.
51	VDD33A	power_in	+3.3V analog power supply.
52	RXP	bidirectional	Ethernet RX data in positive with analog bidirectional signal; may swap with transmit when Auto-MDIX enabled.
53	RXN	bidirectional	Ethernet RX data in negative with analog bidirectional signal; may swap with transmit when Auto-MDIX enabled.
54	VDD33A	power_in	+3.3V analog power supply.
55	TXP	bidirectional	Ethernet TX data out positive with analog bidirectional signal; may swap with receive when Auto-MDIX enabled.
56	TXN	bidirectional	Ethernet TX data out negative with analog bidirectional signal; may swap with receive when Auto-MDIX enabled.
57	VDD33A	power_in	+3.3V analog power supply.
58	USBDM0	bidirectional	Upstream USB DMINUS 0 with analog bidirectional differential signal.
59	USBDP0	bidirectional	Upstream USB DPLUS 0 with analog bidirectional differential signal with integrated pull-up resistor.
60	XO	output	External 25 MHz crystal oscillator output.
61	XI	input	External 25 MHz crystal oscillator input; can also be driven by single-ended clock oscillator.
62	VDD18USBPLL	power_in	USB PLL +1.8V power supply.
63	USBRBIAS	input	External USB bias resistor connection; connect to external 12K 1.0% resistor to ground for HS transmit current and on-chip termination impedance.
64	VDD33A	power_in	+3.3V analog power supply.
65	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-64-EP(9x9)
Category	Interface
Pins	65

CAD (KiCad official)

Symbol: LAN9512I-JZX
Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
3D model files: lan9512i-jzx-etched.step / lan9512i-jzx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lan9512i-jzx.step / lan9512i-jzx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (52 pp, sha256 35af6d6fd0e76bea, retrieved 2026-09-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF