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LAN9512-JZX

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Microchip Tech Ethernet ICs, QFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icslan9512-jzxfactory-2.0.0extractor-text

Verified LAN9512-JZX

by Ray · last 8 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

8 Nov 2026RayPublished by the parts factory: tier mfr, 65 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: LAN9512-JZX · QFN-64-EP(9x9) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 52-page datasheet
  • ✓distributor: lcsc C633506, digikey 638-1086-ND, mouser 886-LAN9512-JZX
  • ✓family: QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-g8dpxd10/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ lan9512-jzx.kicad_sym✓ lan9512-jzx.kicad_mod✓ lan9512-jzx.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1d ago
viewers lan9512-jzx: viewers · Ray 1d ago
lan9512-jzx-etched.glb Publish 0.1.0 · Ray 1d ago
lan9512-jzx-etched.step lan9512-jzx: factory component page (tier=mfr) · Ray 1d ago
lan9512-jzx-hero.glb lan9512-jzx: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
lan9512-jzx-hero.overlay.json Publish 0.1.0 · Ray 1d ago
lan9512-jzx.glb Publish 0.1.0 · Ray 1d ago
lan9512-jzx.kicad_mod Publish 0.1.0 · Ray 1d ago
lan9512-jzx.kicad_sym Publish 0.1.0 · Ray 1d ago
lan9512-jzx.lbr Publish 0.1.0 · Ray 1d ago
lan9512-jzx.step Publish 0.1.0 · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Publish 0.1.0 · Ray 1d ago
verification.json Verified: Published by the parts factory: tier mfr, 65 pins · Ray 1d ago

LAN9512-JZX

Microchip Tech · Ethernet ICs · QFN-64-EP(9x9)

LAN9512-JZX from Microchip Tech, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 USBDM2 bidirectional Downstream USB peripheral 2 DMINUS signal (analog I/O).
2 USBDP2 bidirectional Downstream USB peripheral 2 DPLUS signal (analog I/O).
3 USBDM3 bidirectional Downstream USB peripheral 3 DMINUS signal (analog I/O).
4 USBDP3 bidirectional Downstream USB peripheral 3 DPLUS signal (analog I/O).
5 VDD33A power_in +3.3V analog power supply; see reference schematics for connection.
6 NC unconnected No connect; must be left floating for normal device operation.
7 NC unconnected No connect; must be left floating for normal device operation.
8 NC unconnected No connect; must be left floating for normal device operation.
9 NC unconnected No connect; must be left floating for normal device operation.
10 VDD33A power_in +3.3V analog power supply; see reference schematics for connection.
11 VBUS_DET input 5V-tolerant Schmitt input detecting upstream VBUS power; must be tied to VDD33IO for bus-powered hubs.
12 nRESET input Active-low Schmitt input that resets the device; tie high if unused.
13 TEST1 unconnected Factory test pin; must always be left unconnected.
14 PRTCTL2 bidirectional Port power control output enabling downstream port 2 power, or overcurrent sense input (low indicates overcurrent); IS/OD12 with pull-up.
15 VDD18CORE power_out +1.8V output of the internal core regulator; all VDD18CORE pins must be tied together.
16 PRTCTL3 bidirectional Port power control output enabling downstream port 3 power, or overcurrent sense input (low indicates overcurrent); IS/OD12 with pull-up.
17 NC unconnected No connect; must be left floating for normal device operation.
18 NC unconnected No connect; must be left floating for normal device operation.
19 VDD33IO power_in +3.3V power supply for I/O pins.
20 nFDX_LED/GPIO0 bidirectional Full-duplex LED driven low when link is full-duplex, or GPIO0 programmable as push-pull, open-drain or Schmitt input (OD12, pull-up).
21 nLNKA_LED/GPIO1 bidirectional Link/activity LED driven low on valid link and pulsed high for 80 ms on activity, or GPIO1 programmable as push-pull, open-drain or Schmitt input (OD12, pull-up).
22 nSPD_LED/GPIO2 bidirectional Speed LED driven low at 100 Mbps or during auto-negotiation and high at 10 Mbps, or GPIO2 programmable as push-pull, open-drain or Schmitt input (OD12, pull-up).
23 EECLK output Drives the clock of the external EEPROM (O8).
24 EECS output Drives the chip select of the external EEPROM (O8).
25 EEDO output Drives the EEDI input of the external EEPROM (O8).
26 EEDI input EEPROM data input driven by the EEDO output of the external EEPROM (Schmitt, internal pull-down).
27 VDD33IO power_in +3.3V power supply for I/O pins.
28 nTRST input Active-low JTAG test port reset input; tie high if not used.
29 TMS input JTAG test mode select input.
30 TDI input JTAG test data input.
31 TDO output JTAG test data output (O12).
32 TCK input JTAG test clock input; should be tied high through a 10 kΩ resistor.
33 VDD33IO power_in +3.3V power supply for I/O pins.
34 TEST2 input Factory test pin; must always be connected to VSS for proper operation.
35 GPIO3 bidirectional General purpose I/O programmable as push-pull output, open-drain output or Schmitt input (O8/OD8, pull-up).
36 GPIO4 bidirectional General purpose I/O programmable as push-pull output, open-drain output or Schmitt input (O8/OD8, pull-up).
37 GPIO5 bidirectional General purpose I/O programmable as push-pull output, open-drain output or Schmitt input (O8/OD8, pull-up).
38 VDD18CORE power_out +1.8V output of the internal core regulator; all VDD18CORE pins must be tied together.
39 VDD33IO power_in +3.3V power supply for I/O pins.
40 TEST3 input Factory test pin; must always be connected to VDD33IO for proper operation.
41 AUTOMDIX_EN input Sets default Auto-MDIX: 0 = disabled, 1 = enabled.
42 GPIO6 bidirectional General purpose I/O programmable as push-pull output, open-drain output or Schmitt input (O8/OD8, pull-up).
43 GPIO7 bidirectional General purpose I/O programmable as push-pull output, open-drain output or Schmitt input (O8/OD8, pull-up).
44 CLK24_EN input Enables generation of the 24 MHz clock on the CLK24_OUT pin.
45 CLK24_OUT output Outputs a 24 MHz clock usable as reference clock for a partner hub.
46 VDD33IO power_in +3.3V power supply for I/O pins.
47 TEST4 unconnected Factory test pin; must always be left unconnected.
48 VDD18ETHPLL power_in Ethernet PLL +1.8V power supply; see reference schematics for connection.
49 VDD33A power_in +3.3V analog power supply; see reference schematics for connection.
50 EXRES passive Internal bias circuit pin; connect to an external 12.4K 1.0% resistor to ground.
51 VDD33A power_in +3.3V analog power supply; see reference schematics for connection.
52 RXP bidirectional Positive Ethernet receiver input; may be swapped internally with transmit outputs when Auto-MDIX is enabled.
53 RXN bidirectional Negative Ethernet receiver input; may be swapped internally with transmit outputs when Auto-MDIX is enabled.
54 VDD33A power_in +3.3V analog power supply; see reference schematics for connection.
55 TXP bidirectional Positive Ethernet transmitter output; may be swapped internally with receive inputs when Auto-MDIX is enabled.
56 TXN bidirectional Negative Ethernet transmitter output; may be swapped internally with receive inputs when Auto-MDIX is enabled.
57 VDD33A power_in +3.3V analog power supply; see reference schematics for connection.
58 USBDM0 bidirectional Upstream USB DMINUS signal (analog I/O).
59 USBDP0 bidirectional Upstream USB DPLUS signal (analog I/O).
60 XO output External 25 MHz crystal output; leave unconnected when XI is driven by a single-ended oscillator.
61 XI input External 25 MHz crystal input, or may be driven by a single-ended clock oscillator.
62 VDD18USBPLL power_in USB PLL +1.8V power supply; see reference schematics for connection.
63 USBRBIAS passive Sets HS transmit current level and on-chip termination impedance; connect to an external 12K 1.0% resistor to ground.
64 VDD33A power_in +3.3V analog power supply; see reference schematics for connection.
65 VSS power_in Exposed pad ground on package bottom; must be connected to ground.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-64-EP(9x9)
Category Interface ICs
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (VDD33IO, VDD33A) 0 3.6 V 36
Positive voltage on signal pins, with respect to ground 6 V Note 4-2 36
Negative voltage on signal pins, with respect to ground -0.5 V Note 4-3 36
Positive voltage on XI, with respect to ground 4.6 V 36
Positive voltage on XO, with respect to ground 2.5 V 36
Storage Temperature -55 150 °C 36
HBM ESD Performance -8 8 kV per JESD 22-A114-E 36
Contact Discharge ESD Performance -8 8 kV per IEC61000-4-2 (Note 4-5) 36
Air-Gap Discharge ESD Performance -15 15 kV per IEC61000-4-2 (Note 4-5) 36
Latch-up Performance -200 200 mA per EIA/JESD 78 36
Supply Voltage (VDD33A, VDD33BIAS, VDD33IO) 3.3 V 36
Supply voltage tolerance -300 300 mV around +3.3V supply 36
Ambient Operating Temperature in Still Air TA 0 70 °C commercial version (Note 4-4) 36
Clock input duty cycle 40 50 60 % XI driven by single-ended clock oscillator 43
XI Low Input Level (ICLK Type Buffer) VILI -0.3 0.5 V Note 4-8 40
XI High Input Level (ICLK Type Buffer) VIHI 1.4 3.6 V Note 4-8 40
Negative-Going Threshold (IS Type Input Buffer) VILT 1.01 1.18 1.35 V Schmitt trigger 39
Positive-Going Threshold (IS Type Input Buffer) VIHT 1.39 1.6 1.8 V Schmitt trigger 39
Schmitt Trigger Hysteresis (IS Type Input Buffer) VHYS 345 420 485 mV (VIHT - VILT) 39
Input Leakage (IS Type Input Buffer) IIH -10 10 μA VIN = VSS or VDD33IO 39
Input Leakage (IS_5V Type Input Buffer) IIH 120 μA VIN = 5.5V (Note 4-7) 39
Low Output Level (O8 Type Buffers) VOL 0.4 V IOL = 8mA 39
Low Output Level (OD8 Type Buffer) VOL 0.4 V IOL = 8mA 39
Low Output Level (O12 Type Buffers) VOL 0.4 V IOL = 12mA 39
Low Output Level (OD12 Type Buffer) VOL 0.4 V IOL = 12mA 39
Peak Differential Output Voltage High VPPH 950 1050 mVpk Note 4-9 40
Peak Differential Output Voltage Low VPPL -950 -1050 mVpk Note 4-9 40
Signal Amplitude Symmetry VSS 98 102 % Note 4-9 40
Signal Rise and Fall Time TRF 3 5 nS Note 4-9 40
Rise and Fall Symmetry TRFS 0.5 nS Note 4-9 40
Duty Cycle Distortion DCD 35 50 65 % Note 4-10 40
Overshoot and Undershoot VOS 5 % 40
Jitter 1.4 nS Note 4-11 40
Transmitter Peak Differential Output Voltage VOUT 2.2 2.5 2.8 V Note 4-12 40
Receiver Differential Squelch Threshold VDS 300 420 585 mV 40
TDO output hold from TCK falling edge tdoh 0 ns 41
Frequency Tolerance @ 25°C Ftol -50 50 PPM Note 4-13 43
Frequency Stability Over Temp Ftemp -50 50 PPM Note 4-13 43
Total Allowable PPM Budget -50 50 PPM Note 4-15 43
Drive Level PW 300 uW 43
Equivalent Series Resistance R1 50 Ω 43
Operating Temperature Range (crystal) 0 70 °C commercial version (Notes 4-16, 4-17) 43
nRESET input assertion time 1 μS 41
EECLK Cycle time tckcyc 1110 1130 ns 42
EECLK High time tckh 550 570 ns 42
EECLK Low time tckl 550 570 ns 42
EECS high before rising edge of EECLK tcshckh 1070 ns 42
EECLK falling edge to EECS low tcklcsl 30 ns 42
EEDO valid before rising edge of EECLK tdvckh 550 ns 42
EEDO disable after rising edge EECLK tckhdis 550 ns 42
EEDI setup to rising edge of EECLK tdsckh 90 ns 42
EEDI hold after rising edge of EECLK tdhckh 0 ns 42
EECLK low to data disable (OUTPUT) tckldis 580 ns 42
EEDIO valid after EECS high (VERIFY) tcshdv 600 ns 42
EEDIO hold after EECS low (VERIFY) tdhcsl 0 ns 42
EECS low tcsl 1070 ns 42

CAD (KiCad official)

  • Symbol: LAN9512-JZX
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: lan9512-jzx-etched.step / lan9512-jzx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lan9512-jzx.step / lan9512-jzx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (52 pp, sha256 b6ec2e27273c370b, retrieved 2026-11-08, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF