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LAN9500A-ABZJ-TR

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Microchip Tech USB Converters, QFN-56-EP(8x8). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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LAN9500A-ABZJ-TR

Microchip Tech · USB Converters · QFN-56-EP(8x8)

LAN9500A-ABZJ-TR from Microchip Tech, in a QFN-56-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 nPHY_INT output PHY interrupt output in internal PHY mode (active high, O8) or PHY interrupt input in external PHY mode (active low, IS).
2 TXN bidirectional Ethernet transmit negative differential signal; may be swapped with RXN when Auto-MDIX is enabled.
3 TXP bidirectional Ethernet transmit positive differential signal; may be swapped with RXP when Auto-MDIX is enabled.
4 VDD33A power_in +3.3V analog power supply.
5 RXN bidirectional Ethernet receive negative differential signal; may be swapped with TXN when Auto-MDIX is enabled.
6 RXP bidirectional Ethernet receive positive differential signal; may be swapped with TXP when Auto-MDIX is enabled.
7 NC unconnected No-connect pin for LAN9500A/LAN9500Ai; may be connected to VDD33A for backward compatibility with LAN9500/LAN9500i.
8 EXRES passive External bias resistor connection; connect 12.0K ±1.0% resistor to ground for LAN9500A/LAN9500Ai.
9 VDD33A power_in +3.3V analog power supply.
10 VDDPLL power_in Ethernet PLL power supply; must be connected to VDDCORE for proper operation.
11 USBDM bidirectional USB data minus signal; functionality may be swapped with USBDP via PORT_SWAP configuration strap.
12 USBDP bidirectional USB data plus signal; functionality may be swapped with USBDM via PORT_SWAP configuration strap.
13 TEST2 power_in Test pin; must be connected to VSS for proper operation.
14 NC unconnected No-connect pin; must be left floating for normal device operation.
15 VDD33A power_in +3.3V analog power supply.
16 USBRBIAS passive External USB bias resistor connection; connect 12K ±1.0% resistor to ground for setting HS transmit current and on-chip termination impedance.
17 VDDUSBPLL power_in USB PLL power supply; must be connected to VDDCORE for proper operation.
18 XI input External 25 MHz crystal oscillator input; may alternatively be driven by single-ended clock oscillator.
19 XO output External 25 MHz crystal oscillator output; leave unconnected when XI is driven by single-ended clock.
20 VBUS_DET input USB bus power detection input; 5V tolerant Schmitt-triggered input; for bus-powered applications must be tied to VDD33IO.
21 VDDCORE power_out Digital core power supply output from internal regulator; powers core logic, Ethernet PLL, and USB PLL.
22 MDC/GPIO2 output Management data clock output to external PHY in external PHY mode, or GPIO2 in internal PHY mode.
23 MDIO/GPIO1 bidirectional Management data input/output to/from external PHY in external PHY mode, or GPIO1 in internal PHY mode.
24 nRESET input System reset input; active-low pin allowing external hardware to reset device or signal PME_CLEAR (LAN9500A/LAN9500Ai).
25 VDD33IO power_in +3.3V I/O power supply.
26 nFDX_LED/GPIO8 output Full-duplex indicator LED output driven low when operating in full-duplex mode, or GPIO8 in internal PHY mode.
27 nLNKA_LED/GPIO9 output Link activity indicator LED output driven low for valid link and pulsed for activity, or GPIO9 in internal PHY mode.
28 nSPD_LED/GPIO10 output Speed indicator LED output driven low for 100 Mbps or auto-negotiation, high for 10 Mbps, or GPIO10 in internal PHY mode.
29 EECLK/PWR_SEL output EEPROM clock output to external EEPROM, or PWR_SEL configuration strap determining default bus/self-powered mode.
30 EECS output EEPROM chip select output; may tri-state briefly during power-up; external pull-down resistor recommended.
31 EEDO/AUTOMDIX_EN output EEPROM data output to EEDI input of external EEPROM, or AUTOMDIX_EN configuration strap determining default Auto-MDIX setting.
32 EEDI input EEPROM data input from EEDO output of external EEPROM.
33 TEST3 power_in Test pin; must be connected to VSS for proper operation.
34 PHY_SEL input PHY selection configuration input; 0 selects internal PHY, 1 selects external PHY; internal PHY placed in power down when external mode selected.
35 VDD33IO power_in +3.3V I/O power supply.
36 nTRST/RXD0 input JTAG test port reset input (active low) in internal PHY mode, or RXD0 receive data input in external PHY mode.
37 TDO/nPHY_RST output JTAG test data output in internal PHY mode, or nPHY_RST PHY reset output (active low) in external PHY mode.
38 TCK/RXD1 input JTAG test clock input (maximum 25 MHz) in internal PHY mode, or RXD1 receive data input in external PHY mode.
39 TMS/RXD2 input JTAG test mode select input in internal PHY mode, or RXD2 receive data input in external PHY mode.
40 TDI/RXD3 input JTAG test data input in internal PHY mode, or RXD3 receive data input in external PHY mode.
41 RXCLK input Receive clock input from external PHY in external PHY mode, or internal MII signal (configurable via IME bit) in internal PHY mode.
42 RXDV input Receive data valid input from external PHY in external PHY mode, or internal MII signal (configurable via IME bit) in internal PHY mode.
43 TXEN output Transmit enable output to external PHY indicating valid data on TXD[3:0] in external PHY mode, or internal MII signal in internal PHY mode.
44 RXER input Receive error input from external PHY indicating receive error in packet in external PHY mode, or internal MII signal in internal PHY mode.
45 CRS/GPIO3 bidirectional Carrier sense input from external PHY in external PHY mode, or GPIO3 (programmable input/output) in internal PHY mode.
46 COL/GPIO0 bidirectional MII collision detect input from external PHY in external PHY mode, or GPIO0 (programmable input/output, with PME signaling capability for LAN9500A/LAN9500Ai) in internal PHY mode.
47 TXCLK input Transmit clock input from external PHY in external PHY mode, or internal MII signal (configurable via IME bit) in internal PHY mode.
48 VDD33IO power_in +3.3V I/O power supply.
49 TEST1 power_in Test pin; must be connected to VDD33IO for proper operation.
50 VDDCORE power_out Digital core power supply output from internal regulator; powers core logic, Ethernet PLL, and USB PLL.
51 VDD33IO power_in +3.3V I/O power supply.
52 VDD33IO power_in +3.3V I/O power supply.
53 TXD3/GPIO7/EEP_SIZE output Transmit data 3 output to external PHY in external PHY mode, GPIO7 (programmable with PHY Link Up wake functionality for LAN9500A/LAN9500Ai) in internal PHY mode, or EEP_SIZE configuration strap selecting EEPROM size.
54 TXD2/GPIO6/PORT_SWAP output Transmit data 2 output to external PHY in external PHY mode, GPIO6 (programmable) in internal PHY mode, or PORT_SWAP configuration strap for USB port mapping.
55 TXD1/GPIO5/RMT_WKP output Transmit data 1 output to external PHY in external PHY mode, GPIO5 (programmable) in internal PHY mode, or RMT_WKP configuration strap enabling remote wakeup support.
56 TXD0/GPIO4/EEP_DISABLE output Transmit data 0 output to external PHY in external PHY mode, GPIO4 (programmable) in internal PHY mode, or EEP_DISABLE configuration strap disabling EEPROM autoload.
57 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-56-EP(8x8)
Category Interface
Pins 57

CAD (KiCad official)

  • Symbol: LAN9500A-ABZJ-TR
  • Footprint: Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm
  • 3D model: QFN-56-EP(8x8) (KiCad packages3D, STEP)
  • 3D model files: lan9500a-abzj-tr-etched.step / lan9500a-abzj-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lan9500a-abzj-tr.step / lan9500a-abzj-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (213 pp, sha256 9daaaa5976e22064, retrieved 2026-09-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF