component
LAN9352
Public Made by Adomby adom
Microchip Tech Ethernet ICs, TQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"schema_version": 1,
"type": "component",
"slug": "lan9352",
"title": "LAN9352",
"brief": "Microchip Tech Ethernet ICs, TQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"communication interface chip-uart-485-232",
"lan9352",
"factory-2.0.0",
"extractor-text"
],
"component": {
"mpn": "LAN9352",
"manufacturer": "Microchip Tech",
"package": "TQFP-80(12x12)",
"pin_count": 80,
"category": "Communication Interface Chip/UART/485/232",
"subcategory": "Ethernet ICs",
"datasheet": "https://datasheet.lcsc.com/datasheet/pdf/9e0986d309f7f18cca1ae704956b3cb2.pdf",
"parts": {
"symbol": "lan9352.kicad_sym",
"footprint": "lan9352.kicad_mod",
"model_3d": "lan9352-hero.glb",
"model_3d_plain": "lan9352-etched.glb",
"model_3d_step": "lan9352-etched.step",
"model_3d_step_plain": "lan9352.step",
"lbr": "lan9352.lbr"
},
"distributor_links": {
"lcsc": "C635529"
},
"distributor_check": {
"checked_at": "2026-10-31T12:36:09Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": null,
"status": "no match"
},
"mouser": {
"pn": null,
"status": "no match"
}
},
"pins": [
{
"number": "1",
"name": "OSCI",
"type": "input",
"description": "External 25 MHz crystal input, which can also be driven by a single-ended clock oscillator (leave OSCO unconnected in that case)."
},
{
"number": "2",
"name": "OSCO",
"type": "output",
"description": "External 25 MHz crystal output."
},
{
"number": "3",
"name": "OSCVDD12",
"type": "power_in",
"description": "Crystal +1.2 V power supply, supplied by the on-chip regulator unless configured for regulator off mode via REG_EN."
},
{
"number": "4",
"name": "OSCVSS",
"type": "power_in",
"description": "Crystal ground."
},
{
"number": "5",
"name": "VDD33",
"type": "power_in",
"description": "+3.3 V power supply for the internal regulators; must be supplied even if the internal regulators are disabled."
},
{
"number": "6",
"name": "VDDCR",
"type": "power_in",
"description": "+1.2 V digital core supply, from the on-chip regulator unless in regulator off mode; use 1 µF and 470 pF decoupling capacitors in parallel to ground."
},
{
"number": "7",
"name": "REG_EN",
"type": "input",
"description": "Regulator enable; when tied to 3.3 V the internal 1.2 V regulators are enabled."
},
{
"number": "8",
"name": "FXLOSEN",
"type": "input",
"description": "Three-level strap: below 1 V selects FX-SD/copper for ports A and B, 1.5 V selects FX-LOS for port A only, above 2 V selects FX-LOS for both ports."
},
{
"number": "9",
"name": "FXSDA/FXLOSA/FXSDENA",
"type": "input",
"description": "Port A fiber signal detect (above 2 V typ. is valid signal), loss-of-signal input (high = LOS) in FX-LOS mode, or FX-SD enable strap (above 1 V typ. selects FX-SD)."
},
{
"number": "10",
"name": "FXSDB/FXLOSB/FXSDENB",
"type": "input",
"description": "Port B fiber signal detect (above 2 V typ. is valid signal), loss-of-signal input (high = LOS) in FX-LOS mode, or FX-SD enable strap (above 1 V typ. selects FX-SD)."
},
{
"number": "11",
"name": "RST#",
"type": "input",
"description": "Active-low system reset input with internal pull-up; may be left unconnected since the device has an internal power-on reset."
},
{
"number": "12",
"name": "GPIO7",
"type": "bidirectional",
"description": "General purpose I/O 7, programmable as push-pull output, open-drain output or Schmitt-triggered input, with internal pull-up."
},
{
"number": "13",
"name": "GPIO6",
"type": "bidirectional",
"description": "General purpose I/O 6, programmable as push-pull output, open-drain output or Schmitt-triggered input, with internal pull-up."
},
{
"number": "14",
"name": "D2/AD2/SIO2",
"type": "bidirectional",
"description": "Host bus data bit 2 (indexed mode), address/data bit 2 (multiplexed mode), or SPI/SQI serial data I/O 2."
},
{
"number": "15",
"name": "D1/AD1/SO/SIO1",
"type": "bidirectional",
"description": "Host bus data bit 1 (indexed), address/data bit 1 (multiplexed), SPI serial data output SO or SQI data I/O 1 (with pull-up)."
},
{
"number": "16",
"name": "VDDIO",
"type": "power_in",
"description": "+1.8 V to +3.3 V variable I/O power."
},
{
"number": "17",
"name": "NC",
"type": "unconnected",
"description": "No connect; must be left unconnected for proper operation."
},
{
"number": "18",
"name": "NC",
"type": "unconnected",
"description": "No connect; must be left unconnected for proper operation."
},
{
"number": "19",
"name": "D14/AD14",
"type": "bidirectional",
"description": "Host bus data bit 14 (indexed mode) or address/data bit 14 (multiplexed mode); unused in SPI mode."
},
{
"number": "20",
"name": "D13/AD13",
"type": "bidirectional",
"description": "Host bus data bit 13 (indexed mode) or address/data bit 13 (multiplexed mode); unused in SPI mode."
},
{
"number": "21",
"name": "D0/AD0/SI/SIO0",
"type": "bidirectional",
"description": "Host bus data bit 0 (indexed), address/data bit 0 (multiplexed), SPI serial data input SI or SQI data I/O 0."
},
{
"number": "22",
"name": "PME",
"type": "output",
"description": "Power management event output asserted on a wakeup event; polarity and buffer type (open-drain or push-pull) are programmable."
},
{
"number": "23",
"name": "NC",
"type": "unconnected",
"description": "No connect; must be left unconnected for proper operation."
},
{
"number": "24",
"name": "LED5/GPIO5/PHYADD",
"type": "bidirectional",
"description": "LED 5 output or GPIO5 depending on LED5 enable, also the PHY address configuration strap latched at reset (internal pull-up)."
},
{
"number": "25",
"name": "LED4/GPIO4/1588EN",
"type": "bidirectional",
"description": "LED 4 output or GPIO4 depending on LED4 enable, also the 1588 enable configuration strap latched at reset (internal pull-up)."
},
{
"number": "26",
"name": "D9/AD9/SCK",
"type": "bidirectional",
"description": "Host bus data bit 9 (indexed), address/data bit 9 (multiplexed), or SPI/SQI slave serial clock input."
},
{
"number": "27",
"name": "VDDIO",
"type": "power_in",
"description": "+1.8 V to +3.3 V variable I/O power."
},
{
"number": "28",
"name": "D12/AD12",
"type": "bidirectional",
"description": "Host bus data bit 12 (indexed mode) or address/data bit 12 (multiplexed mode); unused in SPI mode."
},
{
"number": "29",
"name": "D11/AD11",
"type": "bidirectional",
"description": "Host bus data bit 11 (indexed mode) or address/data bit 11 (multiplexed mode); unused in SPI mode."
},
{
"number": "30",
"name": "D10/AD10",
"type": "bidirectional",
"description": "Host bus data bit 10 (indexed mode) or address/data bit 10 (multiplexed mode); unused in SPI mode."
},
{
"number": "31",
"name": "VDDCR",
"type": "power_in",
"description": "+1.2 V digital core supply, from the on-chip regulator unless in regulator off mode."
},
{
"number": "32",
"name": "A1/ALELO",
"type": "input",
"description": "Host bus address bit 1 (indexed mode) or address latch enable low (multiplexed mode) used to load the lower address byte."
},
{
"number": "33",
"name": "A3/MNGT2",
"type": "input",
"description": "Host bus address bit 3 (indexed mode); also host interface configuration strap 2 (MNGT2) latched at reset."
},
{
"number": "34",
"name": "A4/MNGT3",
"type": "input",
"description": "Host bus address bit 4 (indexed mode); also host interface configuration strap 3 (MNGT3, address phase) latched at reset."
},
{
"number": "35",
"name": "CS",
"type": "input",
"description": "Host bus chip select, normally active low, indicating the device is selected for the current transfer."
},
{
"number": "36",
"name": "A2/ALEHI",
"type": "input",
"description": "Host bus address bit 2 (indexed mode) or address latch enable high (multiplexed mode) used to load the higher address byte in dual phase mode."
},
{
"number": "37",
"name": "WR/ENB",
"type": "input",
"description": "Host bus write strobe or data enable strobe, normally active low, polarity set by HBI_wr_en_polarity_strap."
},
{
"number": "38",
"name": "RD/RD_WR",
"type": "input",
"description": "Host bus read strobe or read/write direction control, normally active low read or read when 1, polarity set by HBI_rd_rdwr_polarity_strap."
},
{
"number": "39",
"name": "VDDIO",
"type": "power_in",
"description": "+1.8 V to +3.3 V variable I/O power."
},
{
"number": "40",
"name": "NC",
"type": "unconnected",
"description": "No connect; must be left unconnected for proper operation."
},
{
"number": "41",
"name": "A0/D15/AD15",
"type": "bidirectional",
"description": "Host bus address bit 0 / data bit 15 (indexed mode) or address/data bit 15 (multiplexed mode); address bit 0 is not used in 16-bit data mode."
},
{
"number": "42",
"name": "LED3/GPIO3/EEEEN",
"type": "bidirectional",
"description": "LED 3 output or GPIO3 depending on LED3 enable, also the Energy Efficient Ethernet enable strap latched at reset (internal pull-up)."
},
{
"number": "43",
"name": "FIFOSEL",
"type": "input",
"description": "Directly selects the Host MAC TX and RX data FIFOs for non-multiplexed address mode."
},
{
"number": "44",
"name": "NC",
"type": "unconnected",
"description": "No connect; must be left unconnected for proper operation."
},
{
"number": "45",
"name": "NC",
"type": "unconnected",
"description": "No connect; must be left unconnected for proper operation."
},
{
"number": "46",
"name": "NC",
"type": "unconnected",
"description": "No connect; must be left unconnected for proper operation."
},
{
"number": "47",
"name": "NC",
"type": "unconnected",
"description": "No connect; must be left unconnected for proper operation."
},
{
"number": "48",
"name": "D3/AD3/SIO3",
"type": "bidirectional",
"description": "Host bus data bit 3 (indexed), address/data bit 3 (multiplexed), or SPI/SQI serial data I/O 3."
},
{
"number": "49",
"name": "D6/AD6",
"type": "bidirectional",
"description": "Host bus data bit 6 (indexed mode) or address/data bit 6 (multiplexed mode); unused in SPI mode."
},
{
"number": "50",
"name": "VDDIO",
"type": "power_in",
"description": "+1.8 V to +3.3 V variable I/O power."
},
{
"number": "51",
"name": "VDDCR",
"type": "power_in",
"description": "+1.2 V digital core supply, from the on-chip regulator unless in regulator off mode."
},
{
"number": "52",
"name": "D7/AD7",
"type": "bidirectional",
"description": "Host bus data bit 7 (indexed mode) or address/data bit 7 (multiplexed mode); unused in SPI mode."
},
{
"number": "53",
"name": "D8/AD8",
"type": "bidirectional",
"description": "Host bus data bit 8 (indexed mode) or address/data bit 8 (multiplexed mode); unused in SPI mode."
},
{
"number": "54",
"name": "TESTMODE",
"type": "input",
"description": "Test mode pin with internal pull-down; must be tied to VSS for proper operation."
},
{
"number": "55",
"name": "EESDA/TMS",
"type": "bidirectional",
"description": "EEPROM I2C serial data input/open-drain output (must be pulled up externally at all times), shared with JTAG test mode select TMS."
},
{
"number": "56",
"name": "EESCL/TCK",
"type": "bidirectional",
"description": "EEPROM I2C clock input/open-drain output (must be pulled up externally at all times), shared with JTAG test clock TCK."
},
{
"number": "57",
"name": "IRQ",
"type": "output",
"description": "Interrupt request output with programmable polarity, source and buffer type (open-drain or push-pull)."
},
{
"number": "58",
"name": "LED2/GPIO2/E2PSIZE",
"type": "bidirectional",
"description": "LED 2 output or GPIO2 depending on LED2 enable, also the EEPROM size strap (low = 1K to 16K bits, high = 32K to 512K bits)."
},
{
"number": "59",
"name": "LED1/GPIO1/TDI/MNGT1",
"type": "bidirectional",
"description": "LED 1 output or GPIO1, shared with JTAG data input TDI and host interface configuration strap 1 (MNGT1) latched at reset."
},
{
"number": "60",
"name": "VDDIO",
"type": "power_in",
"description": "+1.8 V to +3.3 V variable I/O power."
},
{
"number": "61",
"name": "LED0/GPIO0/TDO/MNGT0",
"type": "bidirectional",
"description": "LED 0 output or GPIO0, shared with JTAG data output TDO and host interface configuration strap 0 (MNGT0) latched at reset."
},
{
"number": "62",
"name": "D4/AD4",
"type": "bidirectional",
"description": "Host bus data bit 4 (indexed mode) or address/data bit 4 (multiplexed mode); unused in SPI mode."
},
{
"number": "63",
"name": "D5/AD5/SCS#",
"type": "bidirectional",
"description": "Host bus data bit 5 (indexed), address/data bit 5 (multiplexed), or active-low SPI/SQI slave chip select input."
},
{
"number": "64",
"name": "NC",
"type": "unconnected",
"description": "No connect; must be left unconnected for proper operation."
},
{
"number": "65",
"name": "NC",
"type": "unconnected",
"description": "No connect; must be left unconnected for proper operation."
},
{
"number": "66",
"name": "NC",
"type": "unconnected",
"description": "No connect; must be left unconnected for proper operation."
},
{
"number": "67",
"name": "VDD33TXRX1",
"type": "power_in",
"description": "+3.3 V Port A analog power supply."
},
{
"number": "68",
"name": "TXNA",
"type": "bidirectional",
"description": "Port A twisted pair transmit/receive negative channel 1, or fiber transmit negative."
},
{
"number": "69",
"name": "TXPA",
"type": "bidirectional",
"description": "Port A twisted pair transmit/receive positive channel 1, or fiber transmit positive."
},
{
"number": "70",
"name": "RXNA",
"type": "bidirectional",
"description": "Port A twisted pair transmit/receive negative channel 2, or fiber receive negative."
},
{
"number": "71",
"name": "RXPA",
"type": "bidirectional",
"description": "Port A twisted pair transmit/receive positive channel 2, or fiber receive positive."
},
{
"number": "72",
"name": "VDD12TX1",
"type": "power_in",
"description": "Port A transmitter +1.2 V supply from an external supply or the internal regulator; must be tied to VDD12TX2."
},
{
"number": "73",
"name": "RBIAS",
"type": "passive",
"description": "Internal bias reference; connect an external 12.1 kΩ, 1% resistor to ground."
},
{
"number": "74",
"name": "VDD33BIAS",
"type": "power_in",
"description": "+3.3 V master bias power supply."
},
{
"number": "75",
"name": "VDD12TX2",
"type": "power_in",
"description": "Port B transmitter +1.2 V supply from an external supply or the internal regulator; must be tied to VDD12TX1."
},
{
"number": "76",
"name": "RXPB",
"type": "bidirectional",
"description": "Port B twisted pair transmit/receive positive channel 2, or fiber receive positive."
},
{
"number": "77",
"name": "RXNB",
"type": "bidirectional",
"description": "Port B twisted pair transmit/receive negative channel 2, or fiber receive negative."
},
{
"number": "78",
"name": "TXPB",
"type": "bidirectional",
"description": "Port B twisted pair transmit/receive positive channel 1, or fiber transmit positive."
},
{
"number": "79",
"name": "TXNB",
"type": "bidirectional",
"description": "Port B twisted pair transmit/receive negative channel 1, or fiber transmit negative."
},
{
"number": "80",
"name": "VDD33TXRX2",
"type": "power_in",
"description": "+3.3 V Port B analog power supply."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-sonnet-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Datasheet pages provided name the package '80-TQFP-EP' and do not show body size; the 12x12 mm hint ; Pin types for analog twisted-pair/fiber pins (TXP/TXN/RXP/RXN A/B) are AIO per datasheet and mapped ; Exposed pad is not numbered in the datasheet; labeled 'EP'.",
"44/80 pins cited to the wrong page (name found elsewhere): ['1:OSCI@p18', '9:FXSDA/FXLOSA/FXSDENA@p19', '10:FXSDB/FXLOSB/FXSDENB@p20', '12:GPIO7@p24']"
],
"pages_sent": 55,
"cost_usd": 0.5192,
"at": "2026-10-31T12:35:41"
},
"datasheet": {
"url": "https://datasheet.lcsc.com/datasheet/pdf/9e0986d309f7f18cca1ae704956b3cb2.pdf",
"pages": 601,
"sha256": "19a0b748a26a27ae",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 80,
"described": 80,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "lan9352.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
14,
14,
1.1
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "77f4de0ca0c787b8b4416c735fddfcecf5cf4cea0ca3550f96f5c47c8664594c",
"checked": "2026-10-31",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "lan9352-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
14,
14,
1.1
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "058cc8ce1c16cedcca763725092b4a4b780eddc49dec27d8512e63487e2fc52d",
"checked": "2026-10-31",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "Microchip Tech",
"Package": "TQFP-80(12x12)",
"Category": "Communication Interface Chip/UART/485/232",
"Pins": "80"
},
"appearance": {
"contacts": {
"quote": "with the FXSDB pin. As such, the LVPECL levels ensure that the input is greater than 1 V (typ.) and that Signal Detect mode is selected. When TP copper is desired, the Signal Detect input function is ",
"page": 242,
"doc": "ds.pdf",
"material": "copper"
},
"version": 1,
"datasheet_sha256": "19a0b748a26a27aeea1f20c7d9b3197afe5bb7c506c457eb9824a7ba736c826e"
}
},
"variants": [],
"sections": [
"hero",
"viewers",
"readme",
"breadcrumbs",
"info"
],
"discovery_triggers": [
"lan9352"
],
"discovery_pitch": "LAN9352 (Microchip Tech) component page: datasheet pinout, KiCad symbol, footprint and 3D.",
"author": {
"name": "Ray",
"email": "[email protected]"
},
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"lan9352.kicad_sym",
"lan9352.kicad_mod",
"lan9352.glb",
"lan9352.step",
"lan9352.lbr",
"docs/hero.png",
"docs/lan9352-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"lan9352-hero.glb",
"lan9352-hero.overlay.json",
"lan9352-etched.glb"
],
"visibility": {
"public": true
}
}