component

LAN9352

Public Made by Adom

by adom

Microchip Tech Ethernet ICs, TQFP-80(12x12). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232lan9352factory-2.0.0extractor-text

Verified LAN9352

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 80 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: LAN9352 · TQFP-80(12x12) · 80 pins
  • ✓copper: 80 copper pads, none touching another net
  • ✓datasheet: all 80 pin names found in the 601-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: TQFP-80_12x12mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-zru4_r76/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 80 pins = 80 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 80 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ lan9352.kicad_sym✓ lan9352.kicad_mod✓ lan9352.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
lan9352 / README.md
History Download
Ray Publish 0.1.0 f425349 8h ago

LAN9352

Microchip Tech · Ethernet ICs · TQFP-80(12x12)

LAN9352 from Microchip Tech, in a TQFP-80(12x12). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OSCI input External 25 MHz crystal input, which can also be driven by a single-ended clock oscillator (leave OSCO unconnected in that case).
2 OSCO output External 25 MHz crystal output.
3 OSCVDD12 power_in Crystal +1.2 V power supply, supplied by the on-chip regulator unless configured for regulator off mode via REG_EN.
4 OSCVSS power_in Crystal ground.
5 VDD33 power_in +3.3 V power supply for the internal regulators; must be supplied even if the internal regulators are disabled.
6 VDDCR power_in +1.2 V digital core supply, from the on-chip regulator unless in regulator off mode; use 1 µF and 470 pF decoupling capacitors in parallel to ground.
7 REG_EN input Regulator enable; when tied to 3.3 V the internal 1.2 V regulators are enabled.
8 FXLOSEN input Three-level strap: below 1 V selects FX-SD/copper for ports A and B, 1.5 V selects FX-LOS for port A only, above 2 V selects FX-LOS for both ports.
9 FXSDA/FXLOSA/FXSDENA input Port A fiber signal detect (above 2 V typ. is valid signal), loss-of-signal input (high = LOS) in FX-LOS mode, or FX-SD enable strap (above 1 V typ. selects FX-SD).
10 FXSDB/FXLOSB/FXSDENB input Port B fiber signal detect (above 2 V typ. is valid signal), loss-of-signal input (high = LOS) in FX-LOS mode, or FX-SD enable strap (above 1 V typ. selects FX-SD).
11 RST# input Active-low system reset input with internal pull-up; may be left unconnected since the device has an internal power-on reset.
12 GPIO7 bidirectional General purpose I/O 7, programmable as push-pull output, open-drain output or Schmitt-triggered input, with internal pull-up.
13 GPIO6 bidirectional General purpose I/O 6, programmable as push-pull output, open-drain output or Schmitt-triggered input, with internal pull-up.
14 D2/AD2/SIO2 bidirectional Host bus data bit 2 (indexed mode), address/data bit 2 (multiplexed mode), or SPI/SQI serial data I/O 2.
15 D1/AD1/SO/SIO1 bidirectional Host bus data bit 1 (indexed), address/data bit 1 (multiplexed), SPI serial data output SO or SQI data I/O 1 (with pull-up).
16 VDDIO power_in +1.8 V to +3.3 V variable I/O power.
17 NC unconnected No connect; must be left unconnected for proper operation.
18 NC unconnected No connect; must be left unconnected for proper operation.
19 D14/AD14 bidirectional Host bus data bit 14 (indexed mode) or address/data bit 14 (multiplexed mode); unused in SPI mode.
20 D13/AD13 bidirectional Host bus data bit 13 (indexed mode) or address/data bit 13 (multiplexed mode); unused in SPI mode.
21 D0/AD0/SI/SIO0 bidirectional Host bus data bit 0 (indexed), address/data bit 0 (multiplexed), SPI serial data input SI or SQI data I/O 0.
22 PME output Power management event output asserted on a wakeup event; polarity and buffer type (open-drain or push-pull) are programmable.
23 NC unconnected No connect; must be left unconnected for proper operation.
24 LED5/GPIO5/PHYADD bidirectional LED 5 output or GPIO5 depending on LED5 enable, also the PHY address configuration strap latched at reset (internal pull-up).
25 LED4/GPIO4/1588EN bidirectional LED 4 output or GPIO4 depending on LED4 enable, also the 1588 enable configuration strap latched at reset (internal pull-up).
26 D9/AD9/SCK bidirectional Host bus data bit 9 (indexed), address/data bit 9 (multiplexed), or SPI/SQI slave serial clock input.
27 VDDIO power_in +1.8 V to +3.3 V variable I/O power.
28 D12/AD12 bidirectional Host bus data bit 12 (indexed mode) or address/data bit 12 (multiplexed mode); unused in SPI mode.
29 D11/AD11 bidirectional Host bus data bit 11 (indexed mode) or address/data bit 11 (multiplexed mode); unused in SPI mode.
30 D10/AD10 bidirectional Host bus data bit 10 (indexed mode) or address/data bit 10 (multiplexed mode); unused in SPI mode.
31 VDDCR power_in +1.2 V digital core supply, from the on-chip regulator unless in regulator off mode.
32 A1/ALELO input Host bus address bit 1 (indexed mode) or address latch enable low (multiplexed mode) used to load the lower address byte.
33 A3/MNGT2 input Host bus address bit 3 (indexed mode); also host interface configuration strap 2 (MNGT2) latched at reset.
34 A4/MNGT3 input Host bus address bit 4 (indexed mode); also host interface configuration strap 3 (MNGT3, address phase) latched at reset.
35 CS input Host bus chip select, normally active low, indicating the device is selected for the current transfer.
36 A2/ALEHI input Host bus address bit 2 (indexed mode) or address latch enable high (multiplexed mode) used to load the higher address byte in dual phase mode.
37 WR/ENB input Host bus write strobe or data enable strobe, normally active low, polarity set by HBI_wr_en_polarity_strap.
38 RD/RD_WR input Host bus read strobe or read/write direction control, normally active low read or read when 1, polarity set by HBI_rd_rdwr_polarity_strap.
39 VDDIO power_in +1.8 V to +3.3 V variable I/O power.
40 NC unconnected No connect; must be left unconnected for proper operation.
41 A0/D15/AD15 bidirectional Host bus address bit 0 / data bit 15 (indexed mode) or address/data bit 15 (multiplexed mode); address bit 0 is not used in 16-bit data mode.
42 LED3/GPIO3/EEEEN bidirectional LED 3 output or GPIO3 depending on LED3 enable, also the Energy Efficient Ethernet enable strap latched at reset (internal pull-up).
43 FIFOSEL input Directly selects the Host MAC TX and RX data FIFOs for non-multiplexed address mode.
44 NC unconnected No connect; must be left unconnected for proper operation.
45 NC unconnected No connect; must be left unconnected for proper operation.
46 NC unconnected No connect; must be left unconnected for proper operation.
47 NC unconnected No connect; must be left unconnected for proper operation.
48 D3/AD3/SIO3 bidirectional Host bus data bit 3 (indexed), address/data bit 3 (multiplexed), or SPI/SQI serial data I/O 3.
49 D6/AD6 bidirectional Host bus data bit 6 (indexed mode) or address/data bit 6 (multiplexed mode); unused in SPI mode.
50 VDDIO power_in +1.8 V to +3.3 V variable I/O power.
51 VDDCR power_in +1.2 V digital core supply, from the on-chip regulator unless in regulator off mode.
52 D7/AD7 bidirectional Host bus data bit 7 (indexed mode) or address/data bit 7 (multiplexed mode); unused in SPI mode.
53 D8/AD8 bidirectional Host bus data bit 8 (indexed mode) or address/data bit 8 (multiplexed mode); unused in SPI mode.
54 TESTMODE input Test mode pin with internal pull-down; must be tied to VSS for proper operation.
55 EESDA/TMS bidirectional EEPROM I2C serial data input/open-drain output (must be pulled up externally at all times), shared with JTAG test mode select TMS.
56 EESCL/TCK bidirectional EEPROM I2C clock input/open-drain output (must be pulled up externally at all times), shared with JTAG test clock TCK.
57 IRQ output Interrupt request output with programmable polarity, source and buffer type (open-drain or push-pull).
58 LED2/GPIO2/E2PSIZE bidirectional LED 2 output or GPIO2 depending on LED2 enable, also the EEPROM size strap (low = 1K to 16K bits, high = 32K to 512K bits).
59 LED1/GPIO1/TDI/MNGT1 bidirectional LED 1 output or GPIO1, shared with JTAG data input TDI and host interface configuration strap 1 (MNGT1) latched at reset.
60 VDDIO power_in +1.8 V to +3.3 V variable I/O power.
61 LED0/GPIO0/TDO/MNGT0 bidirectional LED 0 output or GPIO0, shared with JTAG data output TDO and host interface configuration strap 0 (MNGT0) latched at reset.
62 D4/AD4 bidirectional Host bus data bit 4 (indexed mode) or address/data bit 4 (multiplexed mode); unused in SPI mode.
63 D5/AD5/SCS# bidirectional Host bus data bit 5 (indexed), address/data bit 5 (multiplexed), or active-low SPI/SQI slave chip select input.
64 NC unconnected No connect; must be left unconnected for proper operation.
65 NC unconnected No connect; must be left unconnected for proper operation.
66 NC unconnected No connect; must be left unconnected for proper operation.
67 VDD33TXRX1 power_in +3.3 V Port A analog power supply.
68 TXNA bidirectional Port A twisted pair transmit/receive negative channel 1, or fiber transmit negative.
69 TXPA bidirectional Port A twisted pair transmit/receive positive channel 1, or fiber transmit positive.
70 RXNA bidirectional Port A twisted pair transmit/receive negative channel 2, or fiber receive negative.
71 RXPA bidirectional Port A twisted pair transmit/receive positive channel 2, or fiber receive positive.
72 VDD12TX1 power_in Port A transmitter +1.2 V supply from an external supply or the internal regulator; must be tied to VDD12TX2.
73 RBIAS passive Internal bias reference; connect an external 12.1 kΩ, 1% resistor to ground.
74 VDD33BIAS power_in +3.3 V master bias power supply.
75 VDD12TX2 power_in Port B transmitter +1.2 V supply from an external supply or the internal regulator; must be tied to VDD12TX1.
76 RXPB bidirectional Port B twisted pair transmit/receive positive channel 2, or fiber receive positive.
77 RXNB bidirectional Port B twisted pair transmit/receive negative channel 2, or fiber receive negative.
78 TXPB bidirectional Port B twisted pair transmit/receive positive channel 1, or fiber transmit positive.
79 TXNB bidirectional Port B twisted pair transmit/receive negative channel 1, or fiber transmit negative.
80 VDD33TXRX2 power_in +3.3 V Port B analog power supply.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-80(12x12)
Category Communication Interface Chip/UART/485/232
Pins 80

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper with the FXSDB pin. As such, the LVPECL levels ensure that the input is greater than 1 V (typ.) and that Signal Detect mode is selected. When TP copper is desired, the Signal Detect input function is 242

CAD (KiCad official)

  • Symbol: LAN9352
  • Footprint: Package_QFP:TQFP-80_12x12mm_P0.5mm
  • 3D model: TQFP-80(12x12) (KiCad packages3D, STEP)
  • 3D model files: lan9352-etched.step / lan9352-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lan9352.step / lan9352.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (601 pp, sha256 19a0b748a26a27ae, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF