LAN9253-I

Microchip Tech · Interface - Specialized · QFN-64(9x9)

LAN9253-I from Microchip Tech, in a QFN-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OSCI	input	External 25 MHz crystal input, which may also be overdriven by a single-ended clock oscillator (leave OSCO unconnected in that case).
2	OSCO	output	External 25 MHz crystal output; left unconnected when OSCI is overdriven by a clock source.
3	OSCVDD12	power_in	+1.2 V crystal oscillator supply, provided by the on-chip regulator unless regulator-off mode is selected via REG_EN.
4	OSCVSS	power_in	Crystal oscillator ground, separate from the common VSS pin.
5	VDD33	power_in	+3.3 V supply for the internal regulators; must be supplied even when the internal regulators are disabled.
6	VDDCR	power_in	+1.2 V digital core supply from the on-chip regulator (or external supply in regulator-off mode); decouple with 1 µF and 470 pF in parallel to ground.
7	REG_EN	input	Regulator enable; when tied to 3.3 V the internal 1.2 V regulators are enabled.
8	CLK_25/CLK_25_EN/XTAL_MODE	bidirectional	25 MHz crystal clock output (O8); CLK_25_EN strap (below 0.8 V disables output, 1.5 V enables it, above 2.2 V selects Schmitt-trigger OSCI input) and XTAL_MODE strap configure it.
9	ERRLED/PME/100FD_B/LEDPOL4	bidirectional	ERR LED output (OD12/OS12, VDD33 domain) whose polarity is set by the LEDPOL4 strap; the pin also carries the 100FD_B strap and an optional PME output.
10	WAIT_ACK/PME/LATCH0/EE_EMUL_SPI3	bidirectional	Host bus wait/acknowledge output (VO8/VOD8), tri-stated when the device is not selected and active low to indicate wait in push-pull mode.
11	RST#	bidirectional	Active-low system reset: an input (VIS/VOD8, pull-up) that may be left unconnected because of the internal POR, and driven low during POR or EtherCAT reset.
12	D2/AD2/SOF/SIO2/EE_EMUL_SPI0	bidirectional	Host bus data bit 2 in non-multiplexed modes (AD2 in multiplexed modes); mapped to the SOF output in Digital I/O mode and SIO2 in SPI mode.
13	D1/AD1/EOF/SO/SIO1	bidirectional	Host bus data bit 1 (AD1 in multiplexed modes); mapped to the EOF output in Digital I/O mode and to SO/SIO1 in SPI mode.
14	VDDIO	power_in	+1.8 V to +3.3 V variable I/O power supply.
15	D14/AD14/DIGIO8/GPI8/GPO8/MII_TXD3/TX_SHIFT1	bidirectional	Host bus data bit 14 (AD14 multiplexed); mapped to DIGIO8/GPIO8 and to MII_TXD3 with the TX_SHIFT1 strap in other modes.
16	D13/AD13/DIGIO7/GPI7/GPO7/MII_TXD2/TX_SHIFT0	bidirectional	Host bus data bit 13 (AD13 multiplexed); mapped to DIGIO7/GPIO7 and to MII_TXD2 with the TX_SHIFT0 strap in other modes.
17	D0/AD0/WD_STATE/SI/SIO0	bidirectional	Host bus data bit 0 (AD0 multiplexed); mapped to SI/SIO0 in SPI modes and to the WD_STATE watchdog state output in Digital I/O mode.
18	SYNC1/LATCH1/PME	bidirectional	EtherCAT SYNC1 output (VO8/VOD8/VOS8) or LATCH1 input (VIS); the SYNC1 output is not driven until the EEPROM is loaded.
19	D9/AD9/LATCH_IN/SCK	bidirectional	Host bus data bit 9 (AD9 multiplexed); mapped to the SCK SPI clock input in SPI modes and to the LATCH_IN external data latch input in Digital I/O mode.
20	VDDIO	power_in	+1.8 V to +3.3 V variable I/O power supply.
21	D12/AD12/DIGIO6/GPI6/GPO6/MII_TXD1/100FD_B	bidirectional	Host bus data bit 12 (AD12 multiplexed); mapped to DIGIO6/GPIO6 and MII_TXD1 (with the 100FD_B strap) in other modes.
22	D11/AD11/DIGIO5/GPI5/GPO5/MII_TXD0/100FD_A	bidirectional	Host bus data bit 11 (AD11 multiplexed); mapped to DIGIO5/GPIO5 and MII_TXD0 (with the 100FD_A strap) in other modes.
23	D10/AD10/DIGIO4/GPI4/GPO4/MII_TXEN	bidirectional	Host bus data bit 10 (AD10 multiplexed); mapped to DIGIO4/GPIO4 and to the MII_TXEN transmit enable output in other modes.
24	VDDCR	power_in	+1.2 V digital core supply from the on-chip regulator or an external source.
25	A1/ALELO/OE_EXT/MII_CLK25/EE_EMUL_SPI2	bidirectional	Host bus address bit 1 (indexed mode) or ALELO address latch (multiplexed mode); OE_EXT output-enable input (low clears outputs) in Digital I/O mode and the MII_CLK25 25 MHz clock output in SPI with MII mode.
26	A3/BE0/DIGIO11/GPI11/GPO11/MII_RXDV	bidirectional	Host bus address bit 3 (indexed mode) or byte enable BE0 (multiplexed mode, active low); mapped to DIGIO11/GPIO11 and MII_RXDV in other modes.
27	A4/BE1/DIGIO12/GPI12/GPO12/MII_RXD0	bidirectional	Host bus address bit 4 (indexed mode) or byte enable BE1 (multiplexed mode, active low); mapped to DIGIO12/GPIO12 and MII_RXD0 in other modes.
28	CS/DIGIO13/GPI13/GPO13/MII_RXD1	bidirectional	Host bus chip select input, normally active low (polarity configurable); mapped to DIGIO13/GPIO13 and MII_RXD1 in other modes.
29	A2/ALEHI/DIGIO10/GPI10/GPO10/LINKACTLED2/EE_EMUL_ALELO_POL/MII_LINKPOL/LEDPOL2	bidirectional	Host bus address bit 2 (indexed mode) or ALEHI address latch enable high (multiplexed mode); mapped to DIGIO10/GPIO10 and LINKACTLED2 in other modes.
30	WR/ENB/DIGIO14/GPI14/GPO14/MII_RXD2	bidirectional	Host bus write strobe WR (normally active low) and ENB data-enable strobe; mapped to DIGIO14/GPIO14 and MII_RXD2 in other modes.
31	RD/RD_WR/DIGIO15/GPI15/GPO15/MII_RXD3	bidirectional	Host bus read strobe RD (normally active low) or RD_WR direction control depending on bus mode; mapped to DIGIO15/GPIO15 and MII_RXD3 in other modes.
32	VDDIO	power_in	+1.8 V to +3.3 V variable I/O power supply.
33	A0/D15/AD15/DIGIO9/GPI9/GPO9/MII_RXER	bidirectional	Host bus address bit 0 (indexed mode, shared with data bit 15); mapped to DIGIO9/GPIO9 and MII_RXER in other modes.
34	SYNC0/LATCH0/PME	bidirectional	EtherCAT SYNC0 output (VO8/VOD8/VOS8) or LATCH0 input (VIS); the SYNC0 output is not driven until the EEPROM is loaded.
35	D3/AD3/WD_TRIG/SIO3/EE_EMUL_SPI1	bidirectional	Host bus data bit 3 (AD3 multiplexed); mapped to the WD_TRIG SyncManager watchdog trigger output in Digital I/O mode and SIO3 in SPI mode.
36	D6/AD6/DIGIO0/GPI0/GPO0/MII_RXCLK	bidirectional	Host bus data bit 6 (AD6 multiplexed); mapped to DIGIO0/GPIO0 and MII_RXCLK receive clock input in other modes.
37	VDDIO	power_in	+1.8 V to +3.3 V variable I/O power supply.
38	VDDCR	power_in	+1.2 V digital core supply from the on-chip regulator or an external source.
39	D7/AD7/DIGIO1/GPI1/GPO1/MII_MDC	bidirectional	Host bus data bit 7 (AD7 multiplexed); mapped to DIGIO1/GPIO1 and the MII_MDC SMI clock output in other modes.
40	D8/AD8/DIGIO2/GPI2/GPO2/MII_MDIO	bidirectional	Host bus data bit 8 (AD8 multiplexed); mapped to DIGIO2/GPIO2 and the MII_MDIO SMI data pin in other modes, which requires an external pull-up.
41	TESTMODE	input	Test mode select; this pin must be tied to VSS for proper operation.
42	EESDA/TMS/EE_EMUL1	bidirectional	EEPROM I2C serial data (VIS/VOD8); must always be pulled up by an external resistor, and also serves as JTAG TMS and the EE_EMUL1 strap.
43	EESCL/TCK/EE_EMUL2	bidirectional	EEPROM I2C serial clock (VIS/VOD8); must be pulled up externally whenever an EEPROM is used, and also serves as JTAG TCK and the EE_EMUL2 strap.
44	IRQ/LATCH1	bidirectional	Interrupt request output (VO8/VOD8) with programmable polarity, source and buffer type; LATCH1 input when the pin is mapped to the latch function.
45	RUNLED/STATE_RUNLED/E2PSIZE/EE_EMUL0/LEDPOL3	bidirectional	RUN LED output (VOD12/VOS12) controlled by the AL Status Register; open-drain/open-source type and polarity are set by strap at reset, and the pin also carries the E2PSIZE strap.
46	LINKACTLED1/TDI/CHIP_MODE1/LEDPOL1	bidirectional	Link/activity LED output for port 1 (VOD12/VOS12); also the JTAG TDI input and the CHIP_MODE1 strap.
47	VDDIO	power_in	+1.8 V to +3.3 V variable I/O power supply.
48	LINKACTLED0/TDO/CHIP_MODE0/100FD_A/LEDPOL0	bidirectional	Link/activity LED output for port 0 (VOD12/VOS12); also the JTAG TDO output and the CHIP_MODE0 and 100FD_A straps.
49	D4/AD4/DIGIO3/GPI3/GPO3/MII_LINK	bidirectional	Host bus data bit 4 (AD4 multiplexed); mapped to DIGIO3/GPIO3 and MII_LINK link status input in other modes.
50	D5/AD5/OUTVALID/SCS#	bidirectional	Host bus data bit 5 (AD5 multiplexed); mapped to the OUTVALID output in Digital I/O mode and to the active-low SCS# SPI chip select input in SPI mode.
51	VDD33TXRX1	power_in	+3.3 V analog power supply for Ethernet PHY A (see Note 3-3).
52	TXNA	bidirectional	Port A twisted-pair transmit/receive negative, channel 1 (AIO), connected to EtherCAT port 0 or 2.
53	TXPA	bidirectional	Port A twisted-pair transmit/receive positive, channel 1 (AIO), connected to EtherCAT port 0 or 2.
54	RXNA	bidirectional	Port A twisted-pair transmit/receive negative, channel 2 (AIO), connected to EtherCAT port 0 or 2.
55	RXPA	bidirectional	Port A twisted-pair transmit/receive positive, channel 2 (AIO), connected to EtherCAT port 0 or 2.
56	VDD12TX1	power_in	+1.2 V Port A transmitter supply; must be tied to VDD12TX2 (pin 59) for proper operation.
57	RBIAS	input	Bias reference for internal circuits; connect to an external 12.1 kΩ, 1% resistor to ground.
58	VDD33BIAS	power_in	+3.3 V bias power supply (see Note 3-3).
59	VDD12TX2	power_in	+1.2 V Port B transmitter supply; must be tied to VDD12TX1 (pin 56) for proper operation.
60	RXPB	bidirectional	Port B twisted-pair transmit/receive positive, channel 2 (AIO), connected to EtherCAT port 1.
61	RXNB	bidirectional	Port B twisted-pair transmit/receive negative, channel 2 (AIO), connected to EtherCAT port 1.
62	TXPB	bidirectional	Port B twisted-pair transmit/receive positive, channel 1 (AIO), connected to EtherCAT port 1.
63	TXNB	bidirectional	Port B twisted-pair transmit/receive negative, channel 1 (AIO), connected to EtherCAT port 1.
64	VDD33TXRX2	power_in	+3.3 V analog power supply for Ethernet PHY B (see Note 3-3).
65	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-64(9x9)
Category	Interface
Pins	65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage (VDD12TX1, VDD12TX2, OSCVDD12, VDDCR) absolute maximum		0		1.5	V		381
Supply Voltage (VDD33TXRX1, VDD33TXRX2, VDD33BIAS, VDD33, VDDIO) absolute maximum		0		3.6	V		381
Ethernet Magnetics Supply Voltage absolute maximum		-0.5		3.6	V		381
Negative voltage on signal pins, with respect to ground		-0.5			V	Note 3 (does not apply to RBIAS)	381
Positive voltage on OSCI, with respect to ground				3.6	V		381
Storage Temperature		-55		150	°C		381
Junction Temperature				150	°C		381
Supply Voltage (VDD12TX1, VDD12TX2, OSCVDD12, VDDCR)		1.14		1.26	V		381
Analog Port Supply Voltage (VDD33TXRX1, VDD33TXRX2, VDD33BIAS, VDD33)		3		3.6	V		381
I/O Supply Voltage (VDDIO)		1.62		3.6	V	Note 1	381
Ethernet Magnetics Supply Voltage		2.25		3.6	V		381
Ambient Operating Temperature in Still Air (industrial version, -I)	TA	-40		85	°C	Note 4: -40°C to +85°C for industrial version	381
Maximum Power Dissipation				766.08	mW	Internal Regulator Enabled, 3.3 V Ethernet Magnetics	382
Input Leakage (non-variable I/O)	IIH	-10		10	µA	VIN = VSS or VDD33	385
Low Output Level, O8 Type Buffers (non-variable)	VOL			0.4	V	IOL = 8 mA	386
Input Leakage (variable I/O)	IIH	-10		10	µA	VIN = VSS or VDDIO	387
Low Output Level, VO8 Type Buffer	VOL			0.4	V	IOL = 8 mA	387
Low Output Level, VOD8 Type Buffer	VOL			0.4	V	IOL = 8 mA	387
Low Output Level, VO12 Type Buffer	VOL			0.4	V	IOL = 12 mA	387
Low Output Level, VOD12 Type Buffer	VOL			0.4	V	IOL = 12 mA	387
Peak Differential Output Voltage High	VPPH	950		1050	mVpk	Note 23	388
Peak Differential Output Voltage Low	VPPL	-950		-1050	mVpk	Note 23	388
Signal Amplitude Symmetry	VSS	98		102	%	Note 23	388
Signal Rise and Fall Time	TRF	3		5	ns	Note 23	388
Rise and Fall Symmetry	TRFS			0.5	ns	Note 23	388
Duty Cycle Distortion	DCD	35	50	65	%	Note 24	388
Overshoot and Undershoot	VOS			5	%		388
Jitter				1.4	ns	Note 25	388
Transmitter Peak Differential Output Voltage (10BASE-T)	VOUT	2.2	2.5	2.8	V	Note 26	388
Receiver Differential Squelch Threshold (10BASE-T)	VDS	300	420	585	mV		388
Frequency Tolerance at 25oC (EtherCAT)	Ftol	-15		15	ppm	EtherCAT, at 25oC	394
Frequency Stability Over Temp (EtherCAT)	Ftemp	-15		15	ppm		394
Total Allowable PPM Budget (EtherCAT)		-25		25	ppm		394
Shunt Capacitance	CO			7	pF		394
Load Capacitance	CL			18	pF		394
Drive Level	PW	300			µW		394
Equivalent Series Resistance	R1			100	Ω		394
Crystal operation output duty cycle (25MHz clock output)		44		57	%	Note 37	395
Crystal override mode output duty cycle distortion		0.76		3.63	%		395
Schmitt trigger mode output duty cycle distortion		-1.03		-1.36	%		395
TCK clock period	ttckp	40			ns		380
TDI, TMS setup to TCK rising edge	tsu	5			ns		380
TDI, TMS hold from TCK rising edge	th	5			ns		380
TDO output valid from TCK falling edge	tdov			15	ns		380
TDO output invalid from TCK falling edge	tdoinvld	0			ns		380
Thermal Resistance Junction to Ambient (still air)	JA		25.6		°C/W	Measured in still air	382
Thermal Resistance Junction to Ambient (airflow 1 m/s)	JA		22.3		°C/W	Airflow 1 m/s	382
Thermal Resistance Junction to Ambient (airflow 2.5 m/s)	JA		20		°C/W	Airflow 2.5 m/s	382
Thermal Resistance Junction to Bottom of Case	JT		0.2		°C/W	Measured in still air	382
Thermal Resistance Junction to Top of Case	JC		2.6		°C/W		382
Ffund (25 MHz crystal fundamental frequency)	Ffund		25		MHz		394

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	abs		slicer error 100BASE-TX is +/-32. A higher absolute slicer error means a degraded signal receiving condition.	199
contacts	copper		The ERRLED pin on the LAN9252 functioned as the fiber mode signal detect as well as the Port A FX-SD Enable. For copper twisted pair operation, this pin would either be tied to or pulled down to groun	275

CAD (KiCad official)

Symbol: LAN9253-I
Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
3D model: QFN-64(9x9) (KiCad packages3D, STEP)
3D model files: lan9253-i-etched.step / lan9253-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lan9253-i.step / lan9253-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (402 pp, sha256 45410c2675e5e050, retrieved 2026-10-17, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# LAN9253-I

**Microchip Tech** · Interface - Specialized · QFN-64(9x9)

LAN9253-I from Microchip Tech, in a QFN-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OSCI | input | External 25 MHz crystal input, which may also be overdriven by a single-ended clock oscillator (leave OSCO unconnected in that case). |
| 2 | OSCO | output | External 25 MHz crystal output; left unconnected when OSCI is overdriven by a clock source. |
| 3 | OSCVDD12 | power_in | +1.2 V crystal oscillator supply, provided by the on-chip regulator unless regulator-off mode is selected via REG_EN. |
| 4 | OSCVSS | power_in | Crystal oscillator ground, separate from the common VSS pin. |
| 5 | VDD33 | power_in | +3.3 V supply for the internal regulators; must be supplied even when the internal regulators are disabled. |
| 6 | VDDCR | power_in | +1.2 V digital core supply from the on-chip regulator (or external supply in regulator-off mode); decouple with 1 µF and 470 pF in parallel to ground. |
| 7 | REG_EN | input | Regulator enable; when tied to 3.3 V the internal 1.2 V regulators are enabled. |
| 8 | CLK_25/CLK_25_EN/XTAL_MODE | bidirectional | 25 MHz crystal clock output (O8); CLK_25_EN strap (below 0.8 V disables output, 1.5 V enables it, above 2.2 V selects Schmitt-trigger OSCI input) and XTAL_MODE strap configure it. |
| 9 | ERRLED/PME/100FD_B/LEDPOL4 | bidirectional | ERR LED output (OD12/OS12, VDD33 domain) whose polarity is set by the LEDPOL4 strap; the pin also carries the 100FD_B strap and an optional PME output. |
| 10 | WAIT_ACK/PME/LATCH0/EE_EMUL_SPI3 | bidirectional | Host bus wait/acknowledge output (VO8/VOD8), tri-stated when the device is not selected and active low to indicate wait in push-pull mode. |
| 11 | RST# | bidirectional | Active-low system reset: an input (VIS/VOD8, pull-up) that may be left unconnected because of the internal POR, and driven low during POR or EtherCAT reset. |
| 12 | D2/AD2/SOF/SIO2/EE_EMUL_SPI0 | bidirectional | Host bus data bit 2 in non-multiplexed modes (AD2 in multiplexed modes); mapped to the SOF output in Digital I/O mode and SIO2 in SPI mode. |
| 13 | D1/AD1/EOF/SO/SIO1 | bidirectional | Host bus data bit 1 (AD1 in multiplexed modes); mapped to the EOF output in Digital I/O mode and to SO/SIO1 in SPI mode. |
| 14 | VDDIO | power_in | +1.8 V to +3.3 V variable I/O power supply. |
| 15 | D14/AD14/DIGIO8/GPI8/GPO8/MII_TXD3/TX_SHIFT1 | bidirectional | Host bus data bit 14 (AD14 multiplexed); mapped to DIGIO8/GPIO8 and to MII_TXD3 with the TX_SHIFT1 strap in other modes. |
| 16 | D13/AD13/DIGIO7/GPI7/GPO7/MII_TXD2/TX_SHIFT0 | bidirectional | Host bus data bit 13 (AD13 multiplexed); mapped to DIGIO7/GPIO7 and to MII_TXD2 with the TX_SHIFT0 strap in other modes. |
| 17 | D0/AD0/WD_STATE/SI/SIO0 | bidirectional | Host bus data bit 0 (AD0 multiplexed); mapped to SI/SIO0 in SPI modes and to the WD_STATE watchdog state output in Digital I/O mode. |
| 18 | SYNC1/LATCH1/PME | bidirectional | EtherCAT SYNC1 output (VO8/VOD8/VOS8) or LATCH1 input (VIS); the SYNC1 output is not driven until the EEPROM is loaded. |
| 19 | D9/AD9/LATCH_IN/SCK | bidirectional | Host bus data bit 9 (AD9 multiplexed); mapped to the SCK SPI clock input in SPI modes and to the LATCH_IN external data latch input in Digital I/O mode. |
| 20 | VDDIO | power_in | +1.8 V to +3.3 V variable I/O power supply. |
| 21 | D12/AD12/DIGIO6/GPI6/GPO6/MII_TXD1/100FD_B | bidirectional | Host bus data bit 12 (AD12 multiplexed); mapped to DIGIO6/GPIO6 and MII_TXD1 (with the 100FD_B strap) in other modes. |
| 22 | D11/AD11/DIGIO5/GPI5/GPO5/MII_TXD0/100FD_A | bidirectional | Host bus data bit 11 (AD11 multiplexed); mapped to DIGIO5/GPIO5 and MII_TXD0 (with the 100FD_A strap) in other modes. |
| 23 | D10/AD10/DIGIO4/GPI4/GPO4/MII_TXEN | bidirectional | Host bus data bit 10 (AD10 multiplexed); mapped to DIGIO4/GPIO4 and to the MII_TXEN transmit enable output in other modes. |
| 24 | VDDCR | power_in | +1.2 V digital core supply from the on-chip regulator or an external source. |
| 25 | A1/ALELO/OE_EXT/MII_CLK25/EE_EMUL_SPI2 | bidirectional | Host bus address bit 1 (indexed mode) or ALELO address latch (multiplexed mode); OE_EXT output-enable input (low clears outputs) in Digital I/O mode and the MII_CLK25 25 MHz clock output in SPI with MII mode. |
| 26 | A3/BE0/DIGIO11/GPI11/GPO11/MII_RXDV | bidirectional | Host bus address bit 3 (indexed mode) or byte enable BE0 (multiplexed mode, active low); mapped to DIGIO11/GPIO11 and MII_RXDV in other modes. |
| 27 | A4/BE1/DIGIO12/GPI12/GPO12/MII_RXD0 | bidirectional | Host bus address bit 4 (indexed mode) or byte enable BE1 (multiplexed mode, active low); mapped to DIGIO12/GPIO12 and MII_RXD0 in other modes. |
| 28 | CS/DIGIO13/GPI13/GPO13/MII_RXD1 | bidirectional | Host bus chip select input, normally active low (polarity configurable); mapped to DIGIO13/GPIO13 and MII_RXD1 in other modes. |
| 29 | A2/ALEHI/DIGIO10/GPI10/GPO10/LINKACTLED2/EE_EMUL_ALELO_POL/MII_LINKPOL/LEDPOL2 | bidirectional | Host bus address bit 2 (indexed mode) or ALEHI address latch enable high (multiplexed mode); mapped to DIGIO10/GPIO10 and LINKACTLED2 in other modes. |
| 30 | WR/ENB/DIGIO14/GPI14/GPO14/MII_RXD2 | bidirectional | Host bus write strobe WR (normally active low) and ENB data-enable strobe; mapped to DIGIO14/GPIO14 and MII_RXD2 in other modes. |
| 31 | RD/RD_WR/DIGIO15/GPI15/GPO15/MII_RXD3 | bidirectional | Host bus read strobe RD (normally active low) or RD_WR direction control depending on bus mode; mapped to DIGIO15/GPIO15 and MII_RXD3 in other modes. |
| 32 | VDDIO | power_in | +1.8 V to +3.3 V variable I/O power supply. |
| 33 | A0/D15/AD15/DIGIO9/GPI9/GPO9/MII_RXER | bidirectional | Host bus address bit 0 (indexed mode, shared with data bit 15); mapped to DIGIO9/GPIO9 and MII_RXER in other modes. |
| 34 | SYNC0/LATCH0/PME | bidirectional | EtherCAT SYNC0 output (VO8/VOD8/VOS8) or LATCH0 input (VIS); the SYNC0 output is not driven until the EEPROM is loaded. |
| 35 | D3/AD3/WD_TRIG/SIO3/EE_EMUL_SPI1 | bidirectional | Host bus data bit 3 (AD3 multiplexed); mapped to the WD_TRIG SyncManager watchdog trigger output in Digital I/O mode and SIO3 in SPI mode. |
| 36 | D6/AD6/DIGIO0/GPI0/GPO0/MII_RXCLK | bidirectional | Host bus data bit 6 (AD6 multiplexed); mapped to DIGIO0/GPIO0 and MII_RXCLK receive clock input in other modes. |
| 37 | VDDIO | power_in | +1.8 V to +3.3 V variable I/O power supply. |
| 38 | VDDCR | power_in | +1.2 V digital core supply from the on-chip regulator or an external source. |
| 39 | D7/AD7/DIGIO1/GPI1/GPO1/MII_MDC | bidirectional | Host bus data bit 7 (AD7 multiplexed); mapped to DIGIO1/GPIO1 and the MII_MDC SMI clock output in other modes. |
| 40 | D8/AD8/DIGIO2/GPI2/GPO2/MII_MDIO | bidirectional | Host bus data bit 8 (AD8 multiplexed); mapped to DIGIO2/GPIO2 and the MII_MDIO SMI data pin in other modes, which requires an external pull-up. |
| 41 | TESTMODE | input | Test mode select; this pin must be tied to VSS for proper operation. |
| 42 | EESDA/TMS/EE_EMUL1 | bidirectional | EEPROM I2C serial data (VIS/VOD8); must always be pulled up by an external resistor, and also serves as JTAG TMS and the EE_EMUL1 strap. |
| 43 | EESCL/TCK/EE_EMUL2 | bidirectional | EEPROM I2C serial clock (VIS/VOD8); must be pulled up externally whenever an EEPROM is used, and also serves as JTAG TCK and the EE_EMUL2 strap. |
| 44 | IRQ/LATCH1 | bidirectional | Interrupt request output (VO8/VOD8) with programmable polarity, source and buffer type; LATCH1 input when the pin is mapped to the latch function. |
| 45 | RUNLED/STATE_RUNLED/E2PSIZE/EE_EMUL0/LEDPOL3 | bidirectional | RUN LED output (VOD12/VOS12) controlled by the AL Status Register; open-drain/open-source type and polarity are set by strap at reset, and the pin also carries the E2PSIZE strap. |
| 46 | LINKACTLED1/TDI/CHIP_MODE1/LEDPOL1 | bidirectional | Link/activity LED output for port 1 (VOD12/VOS12); also the JTAG TDI input and the CHIP_MODE1 strap. |
| 47 | VDDIO | power_in | +1.8 V to +3.3 V variable I/O power supply. |
| 48 | LINKACTLED0/TDO/CHIP_MODE0/100FD_A/LEDPOL0 | bidirectional | Link/activity LED output for port 0 (VOD12/VOS12); also the JTAG TDO output and the CHIP_MODE0 and 100FD_A straps. |
| 49 | D4/AD4/DIGIO3/GPI3/GPO3/MII_LINK | bidirectional | Host bus data bit 4 (AD4 multiplexed); mapped to DIGIO3/GPIO3 and MII_LINK link status input in other modes. |
| 50 | D5/AD5/OUTVALID/SCS# | bidirectional | Host bus data bit 5 (AD5 multiplexed); mapped to the OUTVALID output in Digital I/O mode and to the active-low SCS# SPI chip select input in SPI mode. |
| 51 | VDD33TXRX1 | power_in | +3.3 V analog power supply for Ethernet PHY A (see Note 3-3). |
| 52 | TXNA | bidirectional | Port A twisted-pair transmit/receive negative, channel 1 (AIO), connected to EtherCAT port 0 or 2. |
| 53 | TXPA | bidirectional | Port A twisted-pair transmit/receive positive, channel 1 (AIO), connected to EtherCAT port 0 or 2. |
| 54 | RXNA | bidirectional | Port A twisted-pair transmit/receive negative, channel 2 (AIO), connected to EtherCAT port 0 or 2. |
| 55 | RXPA | bidirectional | Port A twisted-pair transmit/receive positive, channel 2 (AIO), connected to EtherCAT port 0 or 2. |
| 56 | VDD12TX1 | power_in | +1.2 V Port A transmitter supply; must be tied to VDD12TX2 (pin 59) for proper operation. |
| 57 | RBIAS | input | Bias reference for internal circuits; connect to an external 12.1 kΩ, 1% resistor to ground. |
| 58 | VDD33BIAS | power_in | +3.3 V bias power supply (see Note 3-3). |
| 59 | VDD12TX2 | power_in | +1.2 V Port B transmitter supply; must be tied to VDD12TX1 (pin 56) for proper operation. |
| 60 | RXPB | bidirectional | Port B twisted-pair transmit/receive positive, channel 2 (AIO), connected to EtherCAT port 1. |
| 61 | RXNB | bidirectional | Port B twisted-pair transmit/receive negative, channel 2 (AIO), connected to EtherCAT port 1. |
| 62 | TXPB | bidirectional | Port B twisted-pair transmit/receive positive, channel 1 (AIO), connected to EtherCAT port 1. |
| 63 | TXNB | bidirectional | Port B twisted-pair transmit/receive negative, channel 1 (AIO), connected to EtherCAT port 1. |
| 64 | VDD33TXRX2 | power_in | +3.3 V analog power supply for Ethernet PHY B (see Note 3-3). |
| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-64(9x9) |
| Category | Interface |
| Pins | 65 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (VDD12TX1, VDD12TX2, OSCVDD12, VDDCR) absolute maximum |  | 0 |  | 1.5 | V |  | 381 |
| Supply Voltage (VDD33TXRX1, VDD33TXRX2, VDD33BIAS, VDD33, VDDIO) absolute maximum |  | 0 |  | 3.6 | V |  | 381 |
| Ethernet Magnetics Supply Voltage absolute maximum |  | -0.5 |  | 3.6 | V |  | 381 |
| Negative voltage on signal pins, with respect to ground |  | -0.5 |  |  | V | Note 3 (does not apply to RBIAS) | 381 |
| Positive voltage on OSCI, with respect to ground |  |  |  | 3.6 | V |  | 381 |
| Storage Temperature |  | -55 |  | 150 | °C |  | 381 |
| Junction Temperature |  |  |  | 150 | °C |  | 381 |
| Supply Voltage (VDD12TX1, VDD12TX2, OSCVDD12, VDDCR) |  | 1.14 |  | 1.26 | V |  | 381 |
| Analog Port Supply Voltage (VDD33TXRX1, VDD33TXRX2, VDD33BIAS, VDD33) |  | 3 |  | 3.6 | V |  | 381 |
| I/O Supply Voltage (VDDIO) |  | 1.62 |  | 3.6 | V | Note 1 | 381 |
| Ethernet Magnetics Supply Voltage |  | 2.25 |  | 3.6 | V |  | 381 |
| Ambient Operating Temperature in Still Air (industrial version, -I) | TA | -40 |  | 85 | °C | Note 4: -40°C to +85°C for industrial version | 381 |
| Maximum Power Dissipation |  |  |  | 766.08 | mW | Internal Regulator Enabled, 3.3 V Ethernet Magnetics | 382 |
| Input Leakage (non-variable I/O) | IIH | -10 |  | 10 | µA | VIN = VSS or VDD33 | 385 |
| Low Output Level, O8 Type Buffers (non-variable) | VOL |  |  | 0.4 | V | IOL = 8 mA | 386 |
| Input Leakage (variable I/O) | IIH | -10 |  | 10 | µA | VIN = VSS or VDDIO | 387 |
| Low Output Level, VO8 Type Buffer | VOL |  |  | 0.4 | V | IOL = 8 mA | 387 |
| Low Output Level, VOD8 Type Buffer | VOL |  |  | 0.4 | V | IOL = 8 mA | 387 |
| Low Output Level, VO12 Type Buffer | VOL |  |  | 0.4 | V | IOL = 12 mA | 387 |
| Low Output Level, VOD12 Type Buffer | VOL |  |  | 0.4 | V | IOL = 12 mA | 387 |
| Peak Differential Output Voltage High | VPPH | 950 |  | 1050 | mVpk | Note 23 | 388 |
| Peak Differential Output Voltage Low | VPPL | -950 |  | -1050 | mVpk | Note 23 | 388 |
| Signal Amplitude Symmetry | VSS | 98 |  | 102 | % | Note 23 | 388 |
| Signal Rise and Fall Time | TRF | 3 |  | 5 | ns | Note 23 | 388 |
| Rise and Fall Symmetry | TRFS |  |  | 0.5 | ns | Note 23 | 388 |
| Duty Cycle Distortion | DCD | 35 | 50 | 65 | % | Note 24 | 388 |
| Overshoot and Undershoot | VOS |  |  | 5 | % |  | 388 |
| Jitter |  |  |  | 1.4 | ns | Note 25 | 388 |
| Transmitter Peak Differential Output Voltage (10BASE-T) | VOUT | 2.2 | 2.5 | 2.8 | V | Note 26 | 388 |
| Receiver Differential Squelch Threshold (10BASE-T) | VDS | 300 | 420 | 585 | mV |  | 388 |
| Frequency Tolerance at 25oC (EtherCAT) | Ftol | -15 |  | 15 | ppm | EtherCAT, at 25oC | 394 |
| Frequency Stability Over Temp (EtherCAT) | Ftemp | -15 |  | 15 | ppm |  | 394 |
| Total Allowable PPM Budget (EtherCAT) |  | -25 |  | 25 | ppm |  | 394 |
| Shunt Capacitance | CO |  |  | 7 | pF |  | 394 |
| Load Capacitance | CL |  |  | 18 | pF |  | 394 |
| Drive Level | PW | 300 |  |  | µW |  | 394 |
| Equivalent Series Resistance | R1 |  |  | 100 | Ω |  | 394 |
| Crystal operation output duty cycle (25MHz clock output) |  | 44 |  | 57 | % | Note 37 | 395 |
| Crystal override mode output duty cycle distortion |  | 0.76 |  | 3.63 | % |  | 395 |
| Schmitt trigger mode output duty cycle distortion |  | -1.03 |  | -1.36 | % |  | 395 |
| TCK clock period | ttckp | 40 |  |  | ns |  | 380 |
| TDI, TMS setup to TCK rising edge | tsu | 5 |  |  | ns |  | 380 |
| TDI, TMS hold from TCK rising edge | th | 5 |  |  | ns |  | 380 |
| TDO output valid from TCK falling edge | tdov |  |  | 15 | ns |  | 380 |
| TDO output invalid from TCK falling edge | tdoinvld | 0 |  |  | ns |  | 380 |
| Thermal Resistance Junction to Ambient (still air) | JA |  | 25.6 |  | °C/W | Measured in still air | 382 |
| Thermal Resistance Junction to Ambient (airflow 1 m/s) | JA |  | 22.3 |  | °C/W | Airflow 1 m/s | 382 |
| Thermal Resistance Junction to Ambient (airflow 2.5 m/s) | JA |  | 20 |  | °C/W | Airflow 2.5 m/s | 382 |
| Thermal Resistance Junction to Bottom of Case | JT |  | 0.2 |  | °C/W | Measured in still air | 382 |
| Thermal Resistance Junction to Top of Case | JC |  | 2.6 |  | °C/W |  | 382 |
| Ffund (25 MHz crystal fundamental frequency) | Ffund |  | 25 |  | MHz |  | 394 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | abs |  | slicer error 100BASE-TX is +/-32. A higher absolute slicer error means a degraded signal receiving condition. | 199 |
| contacts | copper |  | The ERRLED pin on the LAN9252 functioned as the fiber mode signal detect as well as the Port A FX-SD Enable. For copper twisted pair operation, this pin would either be tied to or pulled down to groun | 275 |

## CAD (KiCad official)

- Symbol: `LAN9253-I`
- Footprint: `Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm`
- 3D model: QFN-64(9x9) (KiCad packages3D, STEP)
- 3D model files: `lan9253-i-etched.step` / `lan9253-i-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lan9253-i.step` / `lan9253-i.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603559276329910272) (402 pp, sha256 `45410c2675e5e050`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lan9253-i-datasheet.pdf)