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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

LAN9220-ABZJ

Microchip Tech · Ethernet Controllers · QFN-56-EP(8x8)

LAN9220-ABZJ from Microchip Tech, in a QFN-56-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD33REG	power_in	+3.3V power supply for internal +1.8V regulator.
2	VDD18CORE	power_out	+1.8V from internal core regulator requiring external 0.01µF bypass and 4.7µF bulk capacitor.
3	GPIO0/nLED1	bidirectional	General purpose I/O 0 or speed indicator LED driven low at 100Mb, high at 10Mb and during autonegotiation.
4	GPIO1/nLED2	bidirectional	General purpose I/O 1 or link and activity indicator LED driven low for link, pulsed high 80ms for activity.
5	GPIO2/nLED3	bidirectional	General purpose I/O 2 or full-duplex indicator LED driven low for full-duplex mode.
6	A7	input	Address line 7 for CSR and FIFO selection.
7	A6	input	Address line 6 for CSR and FIFO selection.
8	A5	input	Address line 5 for CSR and FIFO selection.
9	A4	input	Address line 4 for CSR and FIFO selection.
10	A3	input	Address line 3 for CSR and FIFO selection.
11	A2	input	Address line 2 for CSR and FIFO selection.
12	A1	input	Address line 1 for CSR and FIFO selection.
13	FIFO_SEL	input	When driven high, all accesses route to RX or TX data FIFOs and upper address inputs A[7:3] are ignored.
14	TEST	input	Reserved for internal test purposes; must be grounded or pulled low when VDDVARIO < 3.0V.
15	nRD	input	Active low read strobe indicating a host read cycle.
16	nWR	input	Active low write strobe for write cycles and device wakeup from reduced power states.
17	nCS	input	Active low chip select qualifying read and write operations and device wakeup.
18	VDDVARIO	power_in	Variable voltage I/O logic power supply.
19	D15	bidirectional	Host data bus bit 15 (bidirectional).
20	D14	bidirectional	Host data bus bit 14 (bidirectional).
21	D13	bidirectional	Host data bus bit 13 (bidirectional).
22	D12	bidirectional	Host data bus bit 12 (bidirectional).
23	D11	bidirectional	Host data bus bit 11 (bidirectional).
24	VDDVARIO	power_in	Variable voltage I/O logic power supply.
25	D10	bidirectional	Host data bus bit 10 (bidirectional).
26	D9	bidirectional	Host data bus bit 9 (bidirectional).
27	D8	bidirectional	Host data bus bit 8 (bidirectional).
28	D7	bidirectional	Host data bus bit 7 (bidirectional).
29	D6	bidirectional	Host data bus bit 6 (bidirectional).
30	VDDVARIO	power_in	Variable voltage I/O logic power supply.
31	D5	bidirectional	Host data bus bit 5 (bidirectional).
32	D4	bidirectional	Host data bus bit 4 (bidirectional).
33	D3	bidirectional	Host data bus bit 3 (bidirectional).
34	D2	bidirectional	Host data bus bit 2 (bidirectional).
35	D1	bidirectional	Host data bus bit 1 (bidirectional).
36	D0	bidirectional	Host data bus bit 0 (bidirectional).
37	VDD18CORE	power_out	+1.8V from internal core regulator requiring external 0.01µF bypass and 4.7µF bulk capacitor connection.
38	EEDIO/GPO3	bidirectional	EEPROM data I/O or general purpose output 3; bidirectional for EEPROM interface, output-only for GPIO mode.
39	EECS	output	Serial EEPROM chip select output.
40	EECLK/GPO4	output	Serial EEPROM clock output or general purpose output 4 with internal pull-up; leave unconnected if EEPROM unused.
41	PME	output	Power management event indicator output asserted when wake event is detected.
42	nRESET	input	Active low reset input with weak internal pull-up resetting all logic and registers.
43	IRQ	output	Programmable interrupt request output with configurable polarity, source, and buffer type.
44	TPO-	bidirectional	Transmit pair negative output (normal) or receive pair negative input (reversed with Auto-MDIX).
45	TPO+	bidirectional	Transmit pair positive output (normal) or receive pair positive input (reversed with Auto-MDIX).
46	VDD33A	power_in	+3.3V analog power supply.
47	TPI-	bidirectional	Receive pair negative input (normal) or transmit pair negative output (reversed with Auto-MDIX).
48	TPI+	bidirectional	Receive pair positive input (normal) or transmit pair positive output (reversed with Auto-MDIX).
49	VDD33A	power_in	+3.3V analog power supply.
50	EXRES	input	PHY external bias resistor pin requiring connection to ground through 12.4kΩ ±1% resistor.
51	VDD33A	power_in	+3.3V analog power supply.
52	AMDIX_EN	input	Auto-MDIX enable input; pull high or leave unconnected to enable, pull low to disable Auto-MDIX.
53	VDD18A	power_in	+1.8V analog power supply requiring external connection to VDD18CORE.
54	XTAL2	output	External 25MHz crystal oscillator output pin.
55	XTAL1/CLKIN	input	External 25MHz crystal oscillator input or single-ended TTL clock input with XTAL2 unconnected for clock mode.
56	VDDVARIO	power_in	Variable voltage I/O logic power supply.
57	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-56-EP(8x8)
Category	Interface
Pins	57

CAD (KiCad official)

Symbol: LAN9220-ABZJ
Footprint: Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm
3D model: QFN-56-EP(8x8) (KiCad packages3D, STEP)
3D model files: lan9220-abzj-etched.step / lan9220-abzj-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lan9220-abzj.step / lan9220-abzj.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (142 pp, sha256 d1673f1d65fd57dd, retrieved 2026-09-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF