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LAN8742AI-CZ
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Microchip Tech Ethernet ICs, QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LAN8742AI-CZ
Microchip Tech · Ethernet ICs · QFN-24-EP(4x4)
LAN8742AI-CZ from Microchip Tech, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD2A | power_in | Supplies +3.3 V analog port power to Channel 2 and the internal regulator. |
| 2 | LED2/nINT/nPME/nINTSEL | bidirectional | Multiplexed LED2 output (Link Speed by default) that also serves as nINT/nPME, and when high during reset it enables nINT/REFCLKO as nINT (section 3.8.1.3). |
| 3 | LED1/nINT/nPME/REGOFF | bidirectional | Multiplexed LED1 (Link Activity) output that also serves as nINT/nPME, and whose level during reset selects the internal 1.2 V regulator (REGOFF). |
| 4 | XTAL2 | output | Crystal oscillator output pin (OCLK buffer type). |
| 5 | XTAL1/CLKIN | input | Crystal oscillator input pin (ICLK buffer type) that also accepts an external clock input. |
| 6 | VDDCR | power_in | Supplies +1.2 V digital core power, from the on-chip regulator unless REGOFF disables it, and requires 1 µF and 470 pF decoupling capacitors in parallel to ground. |
| 7 | RXD1/MODE1 | output | Bit 1 of the 2-bit RMII receive data output (VO8, 8 mA), also latched as PHY operating mode configuration strap MODE1 at reset. |
| 8 | RXD0/MODE0 | output | Bit 0 of the 2-bit RMII receive data output (VO8, 8 mA), also latched as PHY operating mode configuration strap MODE0 at reset. |
| 9 | VDDIO | power_in | Provides +1.8 V to +3.3 V variable I/O power. |
| 10 | RXER/PHYAD0 | output | Asserted to indicate that an error was detected in the frame being transferred from the transceiver, and multiplexed with the PHYAD0 address strap. |
| 11 | CRS_DV/MODE2 | bidirectional | Multiplexed pin carrying MODE[2] configuration strap latched at reset (Table 3.5); the CRS_DV function text is not in the supplied pages. |
| 12 | MDIO | bidirectional | Serial management data I/O for the SMI; its electrical limits are not in the supplied pages. |
| 13 | MDC | input | Serial management clock input for the SMI; its timing is specified in section 5.6.5 and its text is not in the supplied pages. |
| 14 | nINT/REFCLKO | bidirectional | Multiplexed nINT or REF_CLK output pin, and nINT is not available on this pin when an external 25 MHz source is used. |
| 15 | nRST | input | Active-low reset input, and configuration straps are latched on power-on reset and on nRST deassertion. |
| 16 | TXEN | input | Indicates that valid transmission data is present on TXD[1:0] (VIS input with internal pull-down). |
| 17 | TXD0 | input | The MAC transmits data to the transceiver using this signal (VIS input). |
| 18 | TXD1 | input | The MAC transmits data to the transceiver using this signal (VIS input). |
| 19 | VDD1A | power_in | Supplies +3.3 V analog port power to Channel 1. |
| 20 | TXN | bidirectional | Negative differential twisted-pair transmit/receive MDI pin that connects to the magnetics and RJ45 per the application diagram. |
| 21 | TXP | bidirectional | Positive differential twisted-pair transmit/receive MDI pin that connects to the magnetics and RJ45 per the application diagram. |
| 22 | RXN | bidirectional | Negative differential twisted-pair receive MDI pin that connects to the magnetics and RJ45 per the application diagram. |
| 23 | RXP | bidirectional | Positive differential twisted-pair receive MDI pin that connects to the magnetics and RJ45 per the application diagram. |
| 24 | RBIAS | passive | Bias resistor connection for the analog circuitry; its value is not in the supplied pages. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-24-EP(4x4) |
| Category | Interface ICs |
| Pins | 25 |
CAD (KiCad official)
- Symbol:
LAN8742AI-CZ - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
lan8742ai-cz-etched.step/lan8742ai-cz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lan8742ai-cz.step/lan8742ai-cz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (132 pp, sha256
7f3c0c1f27c20293, retrieved 2026-10-26, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LAN8742AI-CZ
**Microchip Tech** · Ethernet ICs · QFN-24-EP(4x4)
LAN8742AI-CZ from Microchip Tech, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD2A | power_in | Supplies +3.3 V analog port power to Channel 2 and the internal regulator. |
| 2 | LED2/nINT/nPME/nINTSEL | bidirectional | Multiplexed LED2 output (Link Speed by default) that also serves as nINT/nPME, and when high during reset it enables nINT/REFCLKO as nINT (section 3.8.1.3). |
| 3 | LED1/nINT/nPME/REGOFF | bidirectional | Multiplexed LED1 (Link Activity) output that also serves as nINT/nPME, and whose level during reset selects the internal 1.2 V regulator (REGOFF). |
| 4 | XTAL2 | output | Crystal oscillator output pin (OCLK buffer type). |
| 5 | XTAL1/CLKIN | input | Crystal oscillator input pin (ICLK buffer type) that also accepts an external clock input. |
| 6 | VDDCR | power_in | Supplies +1.2 V digital core power, from the on-chip regulator unless REGOFF disables it, and requires 1 µF and 470 pF decoupling capacitors in parallel to ground. |
| 7 | RXD1/MODE1 | output | Bit 1 of the 2-bit RMII receive data output (VO8, 8 mA), also latched as PHY operating mode configuration strap MODE1 at reset. |
| 8 | RXD0/MODE0 | output | Bit 0 of the 2-bit RMII receive data output (VO8, 8 mA), also latched as PHY operating mode configuration strap MODE0 at reset. |
| 9 | VDDIO | power_in | Provides +1.8 V to +3.3 V variable I/O power. |
| 10 | RXER/PHYAD0 | output | Asserted to indicate that an error was detected in the frame being transferred from the transceiver, and multiplexed with the PHYAD0 address strap. |
| 11 | CRS_DV/MODE2 | bidirectional | Multiplexed pin carrying MODE[2] configuration strap latched at reset (Table 3.5); the CRS_DV function text is not in the supplied pages. |
| 12 | MDIO | bidirectional | Serial management data I/O for the SMI; its electrical limits are not in the supplied pages. |
| 13 | MDC | input | Serial management clock input for the SMI; its timing is specified in section 5.6.5 and its text is not in the supplied pages. |
| 14 | nINT/REFCLKO | bidirectional | Multiplexed nINT or REF_CLK output pin, and nINT is not available on this pin when an external 25 MHz source is used. |
| 15 | nRST | input | Active-low reset input, and configuration straps are latched on power-on reset and on nRST deassertion. |
| 16 | TXEN | input | Indicates that valid transmission data is present on TXD[1:0] (VIS input with internal pull-down). |
| 17 | TXD0 | input | The MAC transmits data to the transceiver using this signal (VIS input). |
| 18 | TXD1 | input | The MAC transmits data to the transceiver using this signal (VIS input). |
| 19 | VDD1A | power_in | Supplies +3.3 V analog port power to Channel 1. |
| 20 | TXN | bidirectional | Negative differential twisted-pair transmit/receive MDI pin that connects to the magnetics and RJ45 per the application diagram. |
| 21 | TXP | bidirectional | Positive differential twisted-pair transmit/receive MDI pin that connects to the magnetics and RJ45 per the application diagram. |
| 22 | RXN | bidirectional | Negative differential twisted-pair receive MDI pin that connects to the magnetics and RJ45 per the application diagram. |
| 23 | RXP | bidirectional | Positive differential twisted-pair receive MDI pin that connects to the magnetics and RJ45 per the application diagram. |
| 24 | RBIAS | passive | Bias resistor connection for the analog circuitry; its value is not in the supplied pages. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-24-EP(4x4) |
| Category | Interface ICs |
| Pins | 25 |
## CAD (KiCad official)
- Symbol: `LAN8742AI-CZ`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm`
- 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files: `lan8742ai-cz-etched.step` / `lan8742ai-cz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lan8742ai-cz.step` / `lan8742ai-cz.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/lan8742ai-cz-datasheet.pdf) (132 pp, sha256 `7f3c0c1f27c20293`, retrieved 2026-10-26, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/lan8742ai-cz-datasheet.pdf)