LAN8741A-EN-TR from Microchip Tech, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD2A	power_in	+3.3 V channel 2 analog port power, supplying channel 2 and the internal regulator; connect per the reference schematic.
2	LED2/nINTSEL	output	LED2 is driven active when the link runs at 100 Mbps and is inactive at 10 Mbps or during line isolation; the nINTSEL strap (pulled up by default) selects nINT, or TXER/TXD4 when pulled low to VSS, on pin 18.
3	LED1/REGOFF	output	LED1 is driven active when a valid link is detected and blinks on activity; the REGOFF strap pulled high to VDD2A disables the internal 1.2 V regulator.
4	XTAL2	output	External crystal output; leave unconnected when a single-ended clock oscillator is used on XTAL1/CLKIN.
5	XTAL1/CLKIN	input	External crystal input, or single-ended clock oscillator input (CLKIN) when an oscillator is used.
6	VDDCR	power_in	+1.2 V digital core supply, provided by the on-chip regulator unless REGOFF selects regulator-off mode; 1 µF and 470 pF decoupling capacitors in parallel to ground should be used.
7	RXCLK/PHYAD1	output	In MII mode this is the receive clock output at 25 MHz (100BASE-TX) or 2.5 MHz (10BASE-T); the PHYAD1 strap sets SMI address bit 1.
8	RXD3/PHYAD2	output	MII receive data bit 3 of 4, sent by the transceiver on the receive path and not used in RMII mode; the PHYAD2 strap sets SMI address bit 2.
9	RXD2/RMIISEL	output	MII receive data bit 2 of 4, not used in RMII mode; the RMIISEL strap selects MII when tied low to VSS and RMII when pulled high to VDDIO.
10	RXD1/MODE1	output	Receive data bit 1 (2 bits in RMII mode) sent by the transceiver; the MODE1 strap combines with MODE0 and MODE2 to set the default PHY mode.
11	RXD0/MODE0	output	Receive data bit 0 (2 bits in RMII mode) sent by the transceiver; the MODE0 strap combines with MODE1 and MODE2 to set the default PHY mode.
12	VDDIO	power_in	+1.8 V to +3.3 V variable I/O power supply.
13	RXER/RXD4/PHYAD0	output	Receive error output asserted when an error is detected in the frame being received; it is RXD4 (MSB of the 5-bit symbol) in symbol interface mode, and the PHYAD0 strap sets SMI address bit 0.
14	CRS	output	MII mode carrier sense output that indicates detection of a carrier.
15	COL/CRS_DV/MODE2	output	COL signals collision detection in MII mode, CRS_DV signals carrier sense/receive data valid in RMII mode, and the MODE2 strap combines with MODE0 and MODE1 to set the default PHY mode.
16	MDIO	bidirectional	Serial Management Interface data input/output, with an internal 50 µA (typical) pull-up.
17	MDC	input	Serial Management Interface clock input; the minimum time between MDC edges is 160 ns and the minimum cycle time is 400 ns.
18	nINT/TXER/TXD4	bidirectional	Active-low interrupt output (open-drain, 8 mA sink) that needs an external pull-up to VDDIO; when nINTSEL is low it instead functions as the TXER/TXD4 transmit input.
19	nRST	input	Active-low system reset input with an internal pull-up; configuration straps are latched on its deassertion.
20	TXCLK	output	MII transmit clock used to latch data from the MAC, at 25 MHz for 100BASE-TX or 2.5 MHz for 10BASE-T; not used in RMII mode.
21	TXEN	input	Indicates valid transmit data is present on TXD[3:0] (only TXD[1:0] in RMII mode); internal pull-down is enabled.
22	TXD0	input	MAC transmit data bit 0 used in all modes; variable-voltage Schmitt-trigger input.
23	TXD1	input	MAC transmit data bit 1 used in all modes; variable-voltage Schmitt-trigger input.
24	TXD2	input	MII transmit data bit 2; must be grounded in RMII mode.
25	TXD3	input	MII transmit data bit 3; must be grounded in RMII mode.
26	RXDV	output	Indicates that recovered and decoded data is available on the RXD pins.
27	VDD1A	power_in	+3.3 V channel 1 analog port power.
28	TXN	bidirectional	Ethernet transmit/receive negative channel 1 analog differential pin.
29	TXP	bidirectional	Ethernet transmit/receive positive channel 1 analog differential pin.
30	RXN	bidirectional	Ethernet transmit/receive negative channel 2 analog differential pin.
31	RXP	bidirectional	Ethernet transmit/receive positive channel 2 analog differential pin.
32	RBIAS	passive	Requires a 12.1 kΩ (1%) resistor to ground; nominal voltage is 1.2 V and the resistor dissipates about 1 mW.
33	VSS	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-32-EP(5x5)
Category	Communication Interface Chip/UART/485/232
Pins	33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage (VDDIO, VDD1A, VDD2A)	VDDIO, VDD1A, VDD2A	-0.5		3.6	V		83
Digital Core Supply Voltage (VDDCR)	VDDCR	-0.5		1.5	V		83
Ethernet Magnetics Supply Voltage		-0.5		3.6	V		83
Negative voltage on input signal pins, with respect to ground		-0.5			V	with respect to ground	83
Positive voltage on XTAL1/CLKIN, with respect to ground	XTAL1/CLKIN			3.6	V	with respect to ground	83
Storage Temperature		-55		150	oC		83
Supply Voltage (VDDIO)	VDDIO	1.62		3.6	V		83
Analog Port Supply Voltage (VDD1A, VDD2A)	VDD1A, VDD2A	3		3.6	V		83
Digital Core Supply Voltage (VDDCR)	VDDCR	1.14		1.26	V		83
Ethernet Magnetics Supply Voltage		2.25		3.6	V		83
Ambient Operating Temperature in Still Air	TA	0		70	oC	Commercial version (see Note 1)	83
Low Input Level (IS Type Input Buffer)	VILI	-0.3			V	Schmitt trigger	85
Input Leakage (IS Type Input Buffer)	IIH	-10		10	µA	VIN = VSS or VDDIO	85
Schmitt Trigger Hysteresis (VIHT - VILT), IS Type	VHYS	336	399	459	mV	Schmitt trigger	85
Low Output Level (O12 buffer)	VOL			0.4	V	IOL = 12 mA	85
Low Input Level (ICLK Type Buffer, XTAL1 Input)	VILI	-0.3		0.35	V	see Note 2	85
High Input Level (ICLK Type Buffer, XTAL1 Input)	VIHI			3.6	V	see Note 2	85
Low Input Level (VIS Type Input Buffer)	VILI	-0.3			V	Schmitt trigger	86
High Input Level (VIS Type Input Buffer)	VIHI			3.6	V	Schmitt trigger	86
Input Leakage (VIS Type Input Buffer)	IIH	-10		10	µA	VIN = VSS or VDDIO	86
Low Output Level (VO8 buffer)	VOL			0.4	V	IOL = 8 mA	86
Low Output Level (VOD8 buffer)	VOL			0.4	V	IOL = 8 mA	86
Peak Differential Output Voltage High	VPPH	950		1050	mVpk	see Note 1	87
Peak Differential Output Voltage Low	VPPL	-1050		-950	mVpk	see Note 1	87
Signal Amplitude Symmetry	VSS	98		102	%	see Note 1	87
Signal Rise and Fall Time	TRF	3		5	ns	see Note 1	87
Rise and Fall Symmetry	TRFS			0.5	ns	see Note 1	87
Duty Cycle Distortion	DCD	35	50	65	%	see Note 2	87
Overshoot and Undershoot	VOS			5	%		87
Jitter				1.4	ns	see Note 3	87
Transmitter Peak Differential Output Voltage	VOUT	2.2	2.5	2.8	V	see Note 1	87
Receiver Differential Squelch Threshold	VDS	300	420	585	mV		87
External power supplies at operational level to nRST deassertion	tpurstd	25			ms		88
External power supplies at operational level to nRST valid	tpurstv	0			ns		88
nRST input assertion time	trstia	100			µs		88
Configuration strap pins setup to nRST deassertion	tcss	200			ns		88
Configuration strap pins hold after nRST deassertion	tcsh	1			ns		88
Output tri-state after nRST assertion	totaa			50	ns		88
Output drive after nRST deassertion	todad			800	ns	see Note 1	88
MDIO (read from PHY) output valid from rising edge of MDC	tval			300	ns		94
MDIO (read from PHY) output invalid from rising edge of MDC	toinvld	0			ns		94
CLKIN Frequency Drift		-50		50	ppm		93
CLKIN Duty Cycle		40		60	%		93
Thermal Resistance (junction to ambient)	ΘJA		47.8		oC/W	Measured in still air from the die to ambient air	83
Junction-to-Top-of-Package	ΨJT		0.7		oC/W	Measured in still air	83

CAD (KiCad official)

Symbol: LAN8741A-EN-TR
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
3D model files: lan8741a-en-tr-etched.step / lan8741a-en-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lan8741a-en-tr.step / lan8741a-en-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (106 pp, sha256 ccee0ad7a5977067, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

LAN8741A-EN-TR

Verified LAN8741A-EN-TR

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3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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