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LAN8720AI-CP-ABC

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Microchip Tech Buffers / Drivers, QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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LAN8720AI-CP-ABC

Microchip Tech · Buffers / Drivers · QFN-24-EP(4x4)

LAN8720AI-CP-ABC from Microchip Tech, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD2A power_in +3.3V analog port power to Channel 2 and the internal 1.2V regulator.
2 LED2/nINTSEL bidirectional Link speed LED output (active when operating at 100Mbps, O12 buffer) that doubles as the nINTSEL strap selecting nINT (floating or pulled to VDD2A, default) or REFCLKO (pulled to VSS) on pin 14.
3 LED1/REGOFF bidirectional Link activity LED output (O12 buffer) that doubles as the REGOFF strap, where pulling it high to VDD2A disables the internal 1.2V regulator and floating or low enables it (default).
4 XTAL2 output External crystal output; leave unconnected when a single-ended clock oscillator drives XTAL1/CLKIN.
5 XTAL1/CLKIN input External crystal input or single-ended clock oscillator input (50MHz REF_CLK in REF_CLK In mode).
6 VDDCR power_in +1.2V digital core power, supplied by the on-chip regulator unless REGOFF disables it; use 1uF and 470pF decoupling capacitors in parallel to ground.
7 RXD1/MODE1 bidirectional Receive data bit 1 output (VO8) that doubles as the MODE1 configuration strap (internal pull-up) setting the default PHY mode.
8 RXD0/MODE0 bidirectional Receive data bit 0 output (VO8) that doubles as the MODE0 configuration strap (internal pull-up) setting the default PHY mode.
9 VDDIO power_in +1.6V to +3.6V variable I/O power.
10 RXER/PHYAD0 bidirectional Receive error output (VO8) that doubles as the PHYAD0 strap (internal pull-down) setting the SMI address to 0 or 1.
11 CRS_DV/MODE2 bidirectional Carrier sense/receive data valid output (VO8) that doubles as the MODE2 configuration strap (internal pull-up) setting the default PHY mode.
12 MDIO bidirectional Serial Management Interface data input/output (VIS/VOD8 buffer).
13 MDC input Serial Management Interface clock input (VIS buffer).
14 nINT/REFCLKO bidirectional Active-low open-drain interrupt output (needs external pull-up to VDDIO) or optional 50MHz reference clock output, selected by the nINTSEL strap.
15 nRST input Active-low system reset input with internal pull-up.
16 TXEN input Transmit enable indicating valid transmission data on TXD[1:0] (internal pull-down).
17 TXD0 input Transmit data bit 0 from the MAC to the transceiver.
18 TXD1 input Transmit data bit 1 from the MAC to the transceiver.
19 VDD1A power_in +3.3V analog port power to Channel 1.
20 TXN bidirectional Ethernet transmit/receive negative channel 1 (analog bidirectional).
21 TXP bidirectional Ethernet transmit/receive positive channel 1 (analog bidirectional).
22 RXN bidirectional Ethernet transmit/receive negative channel 2 (analog bidirectional).
23 RXP bidirectional Ethernet transmit/receive positive channel 2 (analog bidirectional).
24 RBIAS passive Analog input requiring a 12.1k ohm 1% resistor to ground; nominal voltage 1.2V.
25 VSS power_in Common ground exposed pad, which must be connected to the ground plane with a via array.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-24-EP(4x4)
Category Logic ICs
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDDIO VDDIO 1.62 3.6 V 52
Analog Port Supply Voltage VDD1A, VDD2A 3 3.6 V 52
Digital Core Supply Voltage VDDCR 1.08 1.32 V 52
Ethernet Magnetics Supply Voltage 2.25 3.6 V 52
Ambient Operating Temperature (industrial) TA -40 85 °C Still air, industrial version 52
Supply Voltage abs max VDDIO, VDD1A, VDD2A -0.5 3.6 V 52
Digital Core Supply Voltage abs max VDDCR -0.5 1.5 V 52
Ethernet Magnetics Supply Voltage abs max -0.5 3.6 V 52
Positive voltage on signal pins 6 V Wrt ground; not XTAL1/CLKIN, XTAL2, RBIAS 52
Negative voltage on signal pins -0.5 V Wrt ground; not RBIAS 52
Positive voltage on XTAL1/CLKIN 3.6 V Wrt ground 52
Positive voltage on XTAL2 2.5 V Wrt ground 52
Storage Temperature -55 150 °C 52
Latch-up Performance -150 150 mA per EIA/JESD 78 52
IS Negative-Going Threshold VILT 1.01 1.19 1.39 V Schmitt trigger 55
IS Positive-Going Threshold VIHT 1.39 1.59 1.79 V Schmitt trigger 55
IS Schmitt Trigger Hysteresis VHYS 336 399 459 mV VIHT - VILT 55
IS Input Leakage IIH -10 10 uA VIN = VSS or VDDIO 55
IS Input Capacitance CIN 2 pF 55
O12 Low Output Level VOL 0.4 V IOL = 12mA 55
ICLK Low Input Level VILI -0.3 0.35 V XTAL1 input 55
ICLK High Input Level VIHI 0.9 3.6 V XTAL1 input 55
VIS Input Leakage IIH -10 10 uA VIN = VSS or VDDIO 56
VIS Input Capacitance CIN 2 pF 56
VO8 Low Output Level VOL 0.4 V IOL = 8mA 56
VOD8 Low Output Level VOL 0.4 V IOL = 8mA 56
100BASE-TX Peak Differential Output Voltage High VPPH 950 1050 mVpk 56
100BASE-TX Peak Differential Output Voltage Low VPPL -950 -1050 mVpk 56
Signal Amplitude Symmetry VSS 98 102 % 56
Signal Rise and Fall Time TRF 3 5 nS 56
Rise and Fall Symmetry TRFS 0.5 nS 56
Duty Cycle Distortion DCD 35 50 65 % 56
Overshoot and Undershoot VOS 5 % 56
Jitter 1.4 nS 56
10BASE-T Transmitter Peak Differential Output Voltage VOUT 2.2 2.5 2.8 V 57
10BASE-T Receiver Differential Squelch Threshold VDS 300 420 585 mV 57
Power supply turn on time tpon 50 mS 58
Power supply turn off time tpoff 500 mS 58
CLKIN Frequency Drift -50 50 ppm 62
CLKIN Duty Cycle 40 60 % 62
CLKIN Jitter 150 psec p-p, not RMS 62
CLKIN frequency 50 MHz 62
MDC period tclkp 400 ns 62
MDC high time tclkh 160 ns 160 (80%) 62
MDC low time tclkl 160 ns 160 (80%) 62
MDIO output valid from rising edge of MDC tval 300 ns read from PHY 62
MDIO output hold from rising edge of MDC tohold 0 ns read from PHY 62
MDIO setup time to rising edge of MDC tsu 10 ns write to PHY 62
MDIO input hold time after rising edge of MDC tihold 10 ns write to PHY 62
Total Current 100BASE-TX w/ traffic (REF_CLK In) 41 45 49 mA 100BASE-TX /w traffic, REF_CLK In mode 53
Total Current 10BASE-T w/ traffic (REF_CLK In) 20 22 24 mA 10BASE-T /w traffic, REF_CLK In mode 53
Total Current General Power Down (REF_CLK In) 2 2.3 3.4 mA General Power Down, REF_CLK In mode 53

CAD (KiCad official)

  • Symbol: LAN8720AI-CP-ABC
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: lan8720ai-cp-abc-etched.step / lan8720ai-cp-abc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lan8720ai-cp-abc.step / lan8720ai-cp-abc.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (78 pp, sha256 1101ca4301b7c864, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF