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LAN8720A-CP-TR-ABC

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Microchip Tech Ethernet Transceivers, QFN-24-EP(4x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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LAN8720A-CP-TR-ABC

Microchip Tech · Ethernet Transceivers · QFN-24-EP(4x4)

LAN8720A-CP-TR-ABC from Microchip Tech, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD2A power_in +3.3V analog port power to Channel 2 and the internal regulator.
2 LED2/nINTSEL bidirectional Link Speed LED output (active when 100Mbps). Also serves as the nINTSEL configuration strap latched at reset: pulled to VDD2A selects nINT on pin 14 (default); pulled to VSS selects REFCLKO on pin 14. Buffer: O12 output / IS(PU) strap.
3 LED1/REGOFF bidirectional Link Activity LED output (blinks on activity). Also serves as REGOFF configuration strap latched at reset: pulled high to VDD2A disables internal 1.2V regulator (external 1.2V must be supplied to VDDCR); floating/pulled low enables it (default). Buffer: O12 output / IS(PD) strap.
4 XTAL2 output External crystal output. Leave unconnected when using a single-ended clock oscillator on XTAL1/CLKIN. Buffer type OCLK.
5 XTAL1/CLKIN input External 25 MHz crystal input (XTAL1) or single-ended clock oscillator input (CLKIN). Buffer type ICLK.
6 VDDCR power_in +1.2V digital core power supply. Supplied by the on-chip regulator unless configured for regulator-off mode via the REGOFF strap. Use 1 uF and 470 pF decoupling capacitors in parallel to ground.
7 RXD1/MODE1 bidirectional RMII Receive Data bit 1 output to the MAC (VO8). Also serves as MODE1 configuration strap (VIS/PU) latched at reset; combined with MODE0 and MODE2 to set the default PHY operating mode.
8 RXD0/MODE0 bidirectional RMII Receive Data bit 0 output to the MAC (VO8). Also serves as MODE0 configuration strap (VIS/PU) latched at reset; combined with MODE1 and MODE2 to set the default PHY operating mode.
9 VDDIO power_in +1.6V to +3.6V variable I/O power supply for the digital interface pins.
10 RXER/PHYAD0 bidirectional RMII Receive Error output (VO8), asserted when an error is detected in the received frame. Also serves as PHYAD0 configuration strap (VIS/PD) that sets the SMI PHY address at reset.
11 CRS_DV/MODE2 bidirectional Carrier Sense / Receive Data Valid output to the MAC (VO8). Also serves as MODE2 configuration strap (VIS/PU) latched at reset; combined with MODE0 and MODE1 to set the default PHY operating mode.
12 MDIO bidirectional Serial Management Interface (SMI/MIIM) data input/output. Buffer type VIS/VOD8 (open-drain output requires external pull-up to VDDIO).
13 MDC input Serial Management Interface (SMI/MIIM) clock input from the MAC. Buffer type VIS.
14 nINT/REFCLKO output Configurable function: active-low interrupt output (VOD8, open-drain, needs external pull-up to VDDIO) or 50 MHz REFCLKO reference clock output (VO8, derived from 25 MHz crystal). Function is selected by the nINTSEL configuration strap on pin 2.
15 nRST input Active-low system reset input. Buffer type VIS(PU).
16 TXEN input RMII Transmit Enable input from the MAC; indicates that valid transmit data is present on TXD[1:0]. Buffer type VIS(PD).
17 TXD0 input RMII Transmit Data bit 0 input from the MAC. Buffer type VIS.
18 TXD1 input RMII Transmit Data bit 1 input from the MAC. Buffer type VIS.
19 VDD1A power_in +3.3V analog port power to Channel 1.
20 TXN bidirectional Ethernet TX/RX Negative Channel 1 (AIO). Connects to the magnetics/transformer MDI interface.
21 TXP bidirectional Ethernet TX/RX Positive Channel 1 (AIO). Connects to the magnetics/transformer MDI interface.
22 RXN bidirectional Ethernet TX/RX Negative Channel 2 (AIO). Connects to the magnetics/transformer MDI interface.
23 RXP bidirectional Ethernet TX/RX Positive Channel 2 (AIO). Connects to the magnetics/transformer MDI interface.
24 RBIAS passive External 1% bias resistor input. Requires a 12.1 kOhm (1%) resistor to ground; nominal pin voltage 1.2 V, dissipates ~1 mW.
EP VSS power_in Exposed thermal pad on the bottom of the package; common ground. Must be connected to the ground plane with a via array.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-24-EP(4x4)
Category Interface
Pins 25

Ordering variants

Same part, different packaging or reel option.

  • LAN8720A-CP-TR-ABC
  • LAN8720A-CP-TR-ABCCP-ABC

CAD (KiCad official)

  • Symbol: LAN8720A-CP-TR-ABC
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
  • 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: lan8720a-cp-tr-abc-etched.step / lan8720a-cp-tr-abc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lan8720a-cp-tr-abc.step / lan8720a-cp-tr-abc.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (78 pp, sha256 a066b5c955ab5b43, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF