# LAN8710AI-EZK

**Microchip Tech** · Ethernet ICs · QFN-32-EP(5x5)

LAN8710AI-EZK from Microchip Tech, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD2A | power_in | +3.3V channel 2 analog port power, which also supplies the internal regulator. |
| 2 | LED2/nINTSEL | bidirectional | LED2 is driven active when the operating speed is 100Mbps; the nINTSEL strap pulled low selects TXER/TXD4 instead of nINT on pin 18. |
| 3 | LED1/REGOFF | bidirectional | LED1 is driven active on a valid link and blinks on activity; the REGOFF strap pulled high to VDD2A disables the internal 1.2V regulator. |
| 4 | XTAL2 | output | External crystal output, left unconnected when a single-ended clock oscillator drives XTAL1/CLKIN. |
| 5 | XTAL1/CLKIN | input | External crystal input or single-ended clock oscillator input. |
| 6 | VDDCR | power_in | +1.2V digital core supply, provided by the on-chip regulator unless regulator-off mode is configured; 1 uF and 470 pF decoupling capacitors in parallel to ground should be used. |
| 7 | RXCLK/PHYAD1 | bidirectional | In MII mode this is the receive clock output at 25MHz (100BASE-TX) or 2.5MHz (10BASE-T); PHYAD1 strap sets SMI address bit 1. |
| 8 | RXD3/PHYAD2 | bidirectional | MII receive data bit 3, not used in RMII mode; PHYAD2 strap sets SMI address bit 2. |
| 9 | RXD2/RMIISEL | bidirectional | MII receive data bit 2, not used in RMII mode; RMIISEL strap pulled high to VDDIO selects RMII mode and low to VSS selects MII mode. |
| 10 | RXD1/MODE1 | bidirectional | Receive data bit 1 of 4 bits (2 bits in RMII mode); MODE1 strap combined with MODE0 and MODE2 sets the default PHY mode. |
| 11 | RXD0/MODE0 | bidirectional | Receive data bit 0 of 4 bits (2 bits in RMII mode); MODE0 strap combined with MODE1 and MODE2 sets the default PHY mode. |
| 12 | VDDIO | power_in | +1.6V to +3.6V variable I/O power supply. |
| 13 | RXER/RXD4/PHYAD0 | bidirectional | Receive error output asserted when an error is detected in the frame; in Symbol Interface mode it carries RXD4; PHYAD0 strap sets SMI address bit 0. |
| 14 | CRS | output | Carrier sense output indicating carrier detection in MII mode. |
| 15 | COL/CRS_DV/MODE2 | bidirectional | Collision detect output in MII mode, carrier sense/receive data valid in RMII mode; MODE2 strap combined with MODE0 and MODE1 sets the default PHY mode. |
| 16 | MDIO | bidirectional | Serial management interface data input/output, variable voltage open-drain output with 8mA sink. |
| 17 | MDC | input | Serial management interface clock, with a minimum of 160 ns between edges and a minimum cycle time of 400 ns. |
| 18 | nINT/TXER/TXD4 | output | Active low interrupt output that requires an external pull-up to VDDIO; when nINTSEL is pulled low the pin functions as TXER/TXD4. |
| 19 | nRST | input | System reset input, active low. |
| 20 | TXCLK | output | MII transmit clock output at 25MHz (100BASE-TX) or 2.5MHz (10BASE-T); not used in RMII mode. |
| 21 | TXEN | input | Indicates valid transmit data on TXD[3:0]; in RMII mode only TXD[1:0] provide valid data. |
| 22 | TXD0 | input | MAC transmit data bit 0, used in all modes. |
| 23 | TXD1 | input | MAC transmit data bit 1, used in all modes. |
| 24 | TXD2 | input | MAC transmit data bit 2 in MII mode; must be grounded in RMII mode. |
| 25 | TXD3 | input | MAC transmit data bit 3 in MII mode; must be grounded in RMII mode. |
| 26 | RXDV | output | Receive data valid, indicating that recovered and decoded data is available on the RXD pins. |
| 27 | VDD1A | power_in | +3.3V channel 1 analog port power. |
| 28 | TXN | bidirectional | Ethernet transmit/receive negative channel 1, analog bidirectional. |
| 29 | TXP | bidirectional | Ethernet transmit/receive positive channel 1, analog bidirectional. |
| 30 | RXN | bidirectional | Ethernet transmit/receive negative channel 2, analog bidirectional. |
| 31 | RXP | bidirectional | Ethernet transmit/receive positive channel 2, analog bidirectional. |
| 32 | RBIAS | passive | External 1% bias resistor input that requires a 12.1k ohm (1%) resistor to ground, with a nominal voltage of 1.2V. |
| 33 | VSS | power_in | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-32-EP(5x5) |
| Category | Interface ICs |
| Pins | 33 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (VDDIO, VDD1A, VDD2A) | VDDIO, VDD1A, VDD2A | -0.5 |  | 3.6 | V | Note 5-1 | 54 |
| Digital Core Supply Voltage (VDDCR) | VDDCR | -0.5 |  | 1.5 | V | Note 5-1 | 54 |
| Ethernet Magnetics Supply Voltage |  | -0.5 |  | 3.6 | V |  | 54 |
| Negative voltage on signal pins, with respect to ground |  | -0.5 |  |  | V | Note 5-3 | 54 |
| Positive voltage on signal pins, with respect to ground |  |  |  | 6 | V | Note 5-2 | 54 |
| Positive voltage on XTAL1/CLKIN, with respect to ground | XTAL1/CLKIN |  |  | 3.6 | V |  | 54 |
| Positive voltage on XTAL2, with respect to ground | XTAL2 |  |  | 2.5 | V |  | 54 |
| Storage Temperature |  | -55 |  | 150 | oC |  | 54 |
| IEC61000-4-2 Contact Discharge ESD Performance |  | -8 |  | 8 | kV | Note 5-5 | 54 |
| IEC61000-4-2 Air-Gap Discharge ESD Performance |  | -15 |  | 15 | kV | Note 5-5 | 54 |
| Latch-up Performance per EIA/JESD 78 |  | -150 |  | 150 | mA |  | 54 |
| Supply Voltage (VDDIO) | VDDIO | 1.62 |  | 3.6 | V |  | 54 |
| Analog Port Supply Voltage (VDD1A, VDD2A) | VDD1A, VDD2A | 3 |  | 3.6 | V |  | 54 |
| Digital Core Supply Voltage (VDDCR) | VDDCR | 1.08 |  | 1.32 | V |  | 54 |
| Ethernet Magnetics Supply Voltage |  | 2.25 |  | 3.6 | V |  | 54 |
| Ambient Operating Temperature in Still Air (TA) | TA | -40 |  | 85 | oC | Industrial version, Note 5-4 | 54 |
| Low Input Level (ICLK type, XTAL1 input) | VILI | -0.3 |  | 0.35 | V | Note 5-10 | 56 |
| High Input Level (ICLK type, XTAL1 input) | VIHI | 0.9 |  | 3.6 | V | Note 5-10 | 56 |
| Low Output Level (O12 type) | VOL |  |  | 0.4 | V | IOL = 12mA | 56 |
| Input Leakage (IS type) | IIH | -10 |  | 10 | uA | VIN = VSS or VDDIO | 56 |
| Low Output Level (VO8 type) | VOL |  |  | 0.4 | V | IOL = 8mA | 57 |
| Low Output Level (VOD8 type) | VOL |  |  | 0.4 | V | IOL = 8mA | 57 |
| Low Input Level (VIS type) | VILI | -0.3 |  |  | V | Note 5-11 | 57 |
| Peak Differential Output Voltage High | VPPH | 950 |  | 1050 | mVpk | Note 5-12 | 57 |
| Peak Differential Output Voltage Low | VPPL | -950 |  | -1050 | mVpk | Note 5-12 | 57 |
| Signal Amplitude Symmetry | VSS | 98 |  | 102 | % | Note 5-12 | 57 |
| Signal Rise and Fall Time | TRF | 3 |  | 5 | nS | Note 5-12 | 57 |
| Rise and Fall Symmetry | TRFS |  |  | 0.5 | nS | Note 5-12 | 57 |
| Duty Cycle Distortion | DCD | 35 | 50 | 65 | % | Note 5-13 | 57 |
| Overshoot and Undershoot | VOS |  |  | 5 | % |  | 57 |
| Jitter |  |  |  | 1.4 | nS | Note 5-14 | 57 |
| Transmitter Peak Differential Output Voltage | VOUT | 2.2 | 2.5 | 2.8 | V | Note 5-15 | 58 |
| Receiver Differential Squelch Threshold | VDS | 300 | 420 | 585 | mV |  | 58 |
| Power supply turn on time | tpon |  |  | 50 | mS |  | 59 |
| Power supply turn off time | tpoff |  |  | 500 | mS |  | 59 |
| CLKIN frequency (RMII REF_CLK) |  | 50 |  |  | MHz |  | 64 |
| CLKIN Frequency Drift |  | -50 |  | 50 | ppm |  | 64 |
| CLKIN Duty Cycle |  | 40 |  | 60 | % |  | 64 |
| CLKIN Jitter |  |  |  | 150 | psec p-p | not RMS | 64 |
| MDC period | tclkp | 400 |  |  | ns |  | 64 |
| MDC high time | tclkh | 160 |  |  | ns |  | 64 |
| MDC low time | tclkl | 160 |  |  | ns |  | 64 |
| MDIO output valid from rising edge of MDC (read from PHY) | tval |  |  | 300 | ns |  | 64 |
| MDIO output hold from rising edge of MDC (read from PHY) | tohold | 0 |  |  | ns |  | 64 |
| MDIO setup time to rising edge of MDC (write to PHY) | tsu | 10 |  |  | ns |  | 64 |
| MDIO input hold time after rising edge of MDC (write to PHY) | tihold | 10 |  |  | ns |  | 64 |
| Frequency Tolerance @ 25oC (300uW crystal) | Ftol | -50 |  | 50 | PPM | Note 5-26 | 65 |
| Frequency Stability Over Temp (300uW crystal) | Ftemp | -50 |  | 50 | PPM | Note 5-26 | 65 |
| Total Allowable PPM Budget (300uW crystal) |  | -50 |  | 50 | PPM | Note 5-28 | 65 |
| Drive Level (300uW crystal) | PW | 300 |  |  | uW |  | 65 |
| Equivalent Series Resistance (300uW crystal) | R1 |  |  | 30 | Ohm |  | 65 |
| Operating Temperature Range (300uW crystal) |  |  |  | 85 | oC | Note 5-35 | 65 |
| Shunt Capacitance (100uW crystal) | CO |  |  | 5 | pF |  | 66 |
| Load Capacitance (100uW crystal) | CL | 8 |  | 12 | pF |  | 66 |
| Equivalent Series Resistance (100uW crystal) | R1 |  |  | 80 | Ohm |  | 67 |
| XTAL2 Series Resistor (100uW crystal) | Rs | 495 | 500 | 505 | Ohm |  | 67 |
| Drive Level (100uW crystal) | PW |  | 100 |  | uW | Note 5-34 | 66 |

## CAD (KiCad official)

- Symbol: `LAN8710AI-EZK`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`
- 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `lan8710ai-ezk-etched.step` / `lan8710ai-ezk-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lan8710ai-ezk.step` / `lan8710ai-ezk.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/lan8710ai-ezk-datasheet.pdf) (80 pp, sha256 `0f4b8670bcfc7e63`, retrieved 2026-10-27, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lan8710ai-ezk-datasheet.pdf)