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LAN8710A-EZK-TR

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Microchip Tech Ethernet Transceivers, QFN-32-EP(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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LAN8710A-EZK-TR

Microchip Tech · Ethernet Transceivers · QFN-32-EP(5x5)

LAN8710A-EZK-TR from Microchip Tech, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD2A power_in +3.3V analog port power for Channel 2 and the internal 1.2V regulator. Decouple to VSS per reference schematic.
2 LED2/nINTSEL bidirectional LED2 output (O12, active when 100 Mbps link speed). Doubles as the nINTSEL configuration strap latched at reset: floated/pulled to VDD2A selects nINT; pulled low to VSS selects TXER/TXD4 on pin 18.
3 LED1/REGOFF bidirectional LED1 output (O12, driven active on valid link, blinks on activity). Doubles as REGOFF configuration strap: pulled high to VDD2A via external resistor disables the internal 1.2V regulator (external 1.2V must be supplied to VDDCR); floated/low = internal regulator enabled.
4 XTAL2 output 25 MHz crystal oscillator output (OCLK). Leave unconnected when driving XTAL1/CLKIN with a single-ended clock oscillator.
5 XTAL1/CLKIN input 25 MHz crystal input (ICLK) or single-ended clock oscillator input. In RMII mode this pin is also the REF_CLK reference.
6 VDDCR power_in +1.2V digital core power. Supplied by the on-chip regulator by default, or from an external 1.2V rail when REGOFF is asserted. Bypass with 1 µF and 470 pF in parallel to VSS.
7 RXCLK/PHYAD1 bidirectional MII receive clock output (VO8): 25 MHz for 100BASE-TX, 2.5 MHz for 10BASE-T. At reset acts as PHYAD1 configuration strap (VIS, internal PD) combining with PHYAD0/PHYAD2 to set the SMI address.
8 RXD3/PHYAD2 bidirectional MII receive data bit 3 (VO8). Unused in RMII mode. At reset acts as PHYAD2 configuration strap (VIS, PD) contributing to the SMI PHY address.
9 RXD2/RMIISEL bidirectional MII receive data bit 2 (VO8). Unused in RMII mode. At reset acts as RMIISEL configuration strap (VIS, PD): low to VSS selects MII, high to VDDIO selects RMII.
10 RXD1/MODE1 bidirectional MII/RMII receive data bit 1 (VO8). Also acts as MODE1 configuration strap (VIS, PU) combining with MODE0/MODE2 to set the default PHY operating mode (auto-neg / speed / duplex).
11 RXD0/MODE0 bidirectional MII/RMII receive data bit 0 (VO8). Also acts as MODE0 configuration strap (VIS, PU) combining with MODE1/MODE2 to set the default PHY operating mode.
12 VDDIO power_in Variable I/O power supply, +1.6V to +3.6V. Sets the digital I/O voltage level for all VIS/VO8 buffers.
13 RXER/RXD4/PHYAD0 bidirectional MII receive error output (VO8, default) or MII RXD4 in 5B-symbol interface mode. At reset acts as PHYAD0 configuration strap (VIS, PD) contributing to the SMI PHY address. Optional in RMII mode.
14 CRS output MII Carrier Sense output (VO8, internal PD). Asserted to indicate carrier detection in MII mode.
15 COL/CRS_DV/MODE2 bidirectional MII collision detect (COL, VO8) or RMII Carrier Sense / Receive Data Valid (CRS_DV). At reset acts as MODE2 configuration strap (VIS, PU) combining with MODE0/MODE1 to set the default PHY mode.
16 MDIO bidirectional Serial Management Interface (SMI/MDIO) data input/output (VIS/VOD8, open-drain). Requires external pull-up to VDDIO.
17 MDC input Serial Management Interface (SMI) clock input (VIS). Driven by the MAC/host to clock MDIO transactions.
18 nINT/TXER/TXD4 bidirectional Active-low interrupt output (VO8) by default; can be reconfigured via the nINTSEL strap (pin 2) to serve as MII Transmit Error (TXER, VIS+PU) or Symbol Interface TXD4. Requires external pull-up to VDDIO when used as nINT.
19 nRST input Active-low external system reset input (VIS, internal PU). Drives configuration-strap latch on rising edge.
20 TXCLK output MII transmit clock output (VO8). 25 MHz for 100BASE-TX, 2.5 MHz for 10BASE-T. Not used in RMII mode.
21 TXEN input MII/RMII transmit enable input (VIS, internal PD). Asserted by the MAC to indicate valid transmit data on TXD.
22 TXD0 input MII/RMII transmit data bit 0 (VIS). Driven by the MAC to send transmit data to the PHY.
23 TXD1 input MII/RMII transmit data bit 1 (VIS). Driven by the MAC to send transmit data to the PHY.
24 TXD2 input MII transmit data bit 2 (VIS). Used in MII mode only; must be tied to ground in RMII mode.
25 TXD3 input MII transmit data bit 3 (VIS). Used in MII mode only; must be tied to ground in RMII mode.
26 RXDV output MII Receive Data Valid output (VO8). Asserted when recovered and decoded data is available on the RXD lines.
27 VDD1A power_in +3.3V analog port power for Channel 1 (TXP/TXN/RXP/RXN reference).
28 TXN bidirectional Ethernet twisted-pair transmit/receive negative, channel 1 (AIO). Connects to the magnetics MDI interface with the 1:1 isolation transformer.
29 TXP bidirectional Ethernet twisted-pair transmit/receive positive, channel 1 (AIO). Connects to the magnetics MDI interface with the 1:1 isolation transformer.
30 RXN bidirectional Ethernet twisted-pair transmit/receive negative, channel 2 (AIO). Auto-MDIX may swap functionality with channel 1 (TXN).
31 RXP bidirectional Ethernet twisted-pair transmit/receive positive, channel 2 (AIO). Auto-MDIX may swap functionality with channel 1 (TXP).
32 RBIAS passive External 1% bias resistor connection. Requires a 12.1 kΩ (1%) resistor to VSS; nominal pin voltage 1.2V, dissipating ~1 mW.
33 VSS power_in Exposed thermal pad on the bottom of the package. Must be connected to the PCB ground plane via a via array; serves as the device common ground.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-32-EP(5x5)
Category Interface
Pins 33

Ordering variants

Same part, different packaging or reel option.

  • LAN8710A-EZK-TR
  • LAN8710A-EZK-TREZC
  • LAN8710A-EZK-TREZC-TR
  • LAN8710A-EZK-ABC
  • LAN8710A-EZK-TREZC-ABC

CAD (KiCad official)

  • Symbol: LAN8710A-EZK-TR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: lan8710a-ezk-tr-etched.step / lan8710a-ezk-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lan8710a-ezk-tr.step / lan8710a-ezk-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (None pp, sha256 0f4b8670bcfc7e63, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF