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LAN8710A-EZC

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Microchip Tech Ethernet ICs, QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LAN8710A-EZC

Microchip Tech · Ethernet ICs · QFN-32-EP(5x5)

LAN8710A-EZC from Microchip Tech, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD2A power_in +3.3V analog port power to Channel 2 and the internal 1.2V regulator.
2 LED2/nINTSEL bidirectional Link speed LED output (O12, active when operating at 100Mbps) that doubles as the nINTSEL strap selecting nINT (floated or pulled to VDD2A) or TXER/TXD4 (pulled low) on pin 18.
3 LED1/REGOFF bidirectional Link activity LED output (O12) that doubles as the REGOFF strap; pulling it high to VDD2A disables the internal 1.2V regulator, floating or low enables it.
4 XTAL2 output External crystal output; leave unconnected when using a single-ended clock oscillator.
5 XTAL1/CLKIN input External crystal input or single-ended clock oscillator input (REF_CLK in RMII mode).
6 VDDCR power_in +1.2V digital core power, supplied by the on-chip regulator unless REGOFF disables it; use 1uF and 470pF decoupling capacitors in parallel to ground.
7 RXCLK/PHYAD1 bidirectional MII receive clock output (25MHz at 100BASE-TX, 2.5MHz at 10BASE-T) that doubles as the PHY address bit 1 configuration strap (internal pull-down).
8 RXD3/PHYAD2 bidirectional MII receive data bit 3 output that doubles as the PHY address bit 2 configuration strap (internal pull-down); not used in RMII mode.
9 RXD2/RMIISEL bidirectional MII receive data bit 2 output that doubles as the MII/RMII select strap (low to VSS selects MII, high to VDDIO selects RMII; internal pull-down).
10 RXD1/MODE1 bidirectional Receive data bit 1 output that doubles as the PHY operating mode bit 1 configuration strap (internal pull-up).
11 RXD0/MODE0 bidirectional Receive data bit 0 output that doubles as the PHY operating mode bit 0 configuration strap (internal pull-up).
12 VDDIO power_in +1.6V to +3.6V variable I/O power.
13 RXER/RXD4/PHYAD0 bidirectional Receive error output (optional in RMII mode), RXD4 in Symbol Interface mode, and PHY address bit 0 configuration strap (internal pull-down).
14 CRS output MII carrier sense output indicating detection of a carrier (internal pull-down).
15 COL/CRS_DV/MODE2 bidirectional Collision detect output in MII mode or carrier sense/receive data valid output in RMII mode, doubling as the PHY operating mode bit 2 configuration strap (internal pull-up).
16 MDIO bidirectional Serial Management Interface data input/output (open-drain output).
17 MDC input Serial Management Interface clock input.
18 nINT/TXER/TXD4 bidirectional Active-low interrupt output (external pull-up to VDDIO) or MII transmit error/TXD4 input depending on the nINTSEL strap.
19 nRST input Active-low system reset input with internal pull-up.
20 TXCLK output MII transmit clock output (25MHz at 100BASE-TX, 2.5MHz at 10BASE-T); not used in RMII mode.
21 TXEN input Transmit enable indicating valid transmit data on TXD[3:0] (only TXD[1:0] in RMII mode), internal pull-down.
22 TXD0 input Transmit data bit 0 from the MAC, used in all modes.
23 TXD1 input Transmit data bit 1 from the MAC, used in all modes.
24 TXD2 input Transmit data bit 2 from the MAC in MII mode; must be grounded in RMII mode.
25 TXD3 input Transmit data bit 3 from the MAC in MII mode; must be grounded in RMII mode.
26 RXDV output Receive data valid output indicating recovered and decoded data is available on the RXD pins.
27 VDD1A power_in +3.3V analog port power to Channel 1.
28 TXN bidirectional Ethernet transmit/receive negative channel 1 analog pin.
29 TXP bidirectional Ethernet transmit/receive positive channel 1 analog pin.
30 RXN bidirectional Ethernet transmit/receive negative channel 2 analog pin.
31 RXP bidirectional Ethernet transmit/receive positive channel 2 analog pin.
32 RBIAS passive Analog reference input requiring a 12.1k ohm (1%) resistor to ground; nominal voltage 1.2V.
33 VSS power_in Common ground exposed pad, which must be connected to the ground plane with a via array.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-32-EP(5x5)
Category Communication Interface Chip/UART/485/232
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (VDDIO, VDD1A, VDD2A) -0.5 3.6 V 54
Digital Core Supply Voltage (VDDCR) VDDCR -0.5 1.5 V 54
Ethernet Magnetics Supply Voltage -0.5 3.6 V 54
Positive voltage on signal pins 6 V with respect to ground; not XTAL1/CLKIN, XTAL2, RBIAS 54
Negative voltage on signal pins -0.5 V with respect to ground; not RBIAS 54
Positive voltage on XTAL1/CLKIN 3.6 V with respect to ground 54
Positive voltage on XTAL2 2.5 V with respect to ground 54
Storage Temperature -55 150 °C 54
Supply Voltage (VDDIO) VDDIO 1.62 3.6 V 54
Analog Port Supply Voltage (VDD1A, VDD2A) VDD1A, VDD2A 3 3.6 V 54
Digital Core Supply Voltage (VDDCR) VDDCR 1.08 1.32 V 54
Ethernet Magnetics Supply Voltage 2.25 3.6 V 54
Ambient Operating Temperature in Still Air TA 0 85 °C extended commercial version 54
IS Low Input Level VILI -0.3 V Schmitt trigger 56
IS High Input Level VIHI 3.6 V Schmitt trigger 56
IS Negative-Going Threshold VILT 1.01 1.19 1.39 V 56
IS Positive-Going Threshold VIHT 1.39 1.59 1.79 V 56
IS Schmitt Trigger Hysteresis VHYS 336 399 459 mV VIHT - VILT 56
IS Input Leakage IIH -10 10 uA VIN = VSS or VDDIO 56
IS Input Capacitance CIN 2 pF 56
O12 Low Output Level VOL 0.4 V IOL = 12mA 56
ICLK Low Input Level (XTAL1) VILI -0.3 0.35 V 56
ICLK High Input Level (XTAL1) VIHI 0.9 3.6 V 56
VIS Low Input Level VILI -0.3 V Schmitt trigger 57
VIS High Input Level VIHI 3.6 V Schmitt trigger 57
VIS Input Leakage IIH -10 10 uA VIN = VSS or VDDIO 57
VIS Input Capacitance CIN 2 pF 57
VO8 Low Output Level VOL 0.4 V IOL = 8mA 57
VOD8 Low Output Level VOL 0.4 V IOL = 8mA 57
Peak Differential Output Voltage High VPPH 950 1050 mVpk 100BASE-TX; measured at line side of transformer, line replaced by 100 (+/- 1%) resistor 57
Peak Differential Output Voltage Low VPPL -950 -1050 mVpk 100BASE-TX; measured at line side of transformer, line replaced by 100 (+/- 1%) resistor 57
Signal Amplitude Symmetry VSS 98 102 % 100BASE-TX 57
Signal Rise and Fall Time TRF 3 5 nS 100BASE-TX 57
Rise and Fall Symmetry TRFS 0.5 nS 100BASE-TX 57
Duty Cycle Distortion DCD 35 50 65 % Offset from 16nS pulse width at 50% of pulse peak 57
Overshoot and Undershoot VOS 5 % 100BASE-TX 57
Jitter 1.4 nS 100BASE-TX; measured differentially 57
Transmitter Peak Differential Output Voltage VOUT 2.2 2.5 2.8 V 10BASE-T; measured with 100 resistive load 58
Receiver Differential Squelch Threshold VDS 300 420 585 mV 10BASE-T 58
Power supply turn on time tpon 50 mS 59
Power supply turn off time tpoff 500 mS 59
MDC period tclkp 400 ns 64
MDIO output valid from rising edge of MDC tval 300 ns read from PHY 64
MDIO setup time to rising edge of MDC tsu 10 ns write to PHY 64
MDIO input hold time after rising edge of MDC tihold 10 ns write to PHY 64
Total Current, 100BASE-TX with traffic 43 48 54 mA VDDIO=1.8V & internal regulator disabled 55
Total Current, 10BASE-T with traffic 20.4 21.2 24.1 mA VDDIO=1.8V & internal regulator disabled 55
Total Current, Energy Detect Power Down 5.2 5.9 7.8 mA VDDIO=1.8V & internal regulator disabled 55
Total Current, General Power Down 1.4 1.7 3.3 mA VDDIO=1.8V & internal regulator disabled 55

CAD (KiCad official)

  • Symbol: LAN8710A-EZC
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: lan8710a-ezc-etched.step / lan8710a-ezc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lan8710a-ezc.step / lan8710a-ezc.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (80 pp, sha256 0f4b8670bcfc7e63, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF