component
LAN7850T-I
Public Made by Adomby adom
Microchip Tech Ethernet Controllers, QFN-56-EP(8x8). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLAN7850T-I
Microchip Tech · Ethernet Controllers · QFN-56-EP(8x8)
LAN7850T-I from Microchip Tech, in a QFN-56-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TR0P | bidirectional | Gigabit Ethernet transmit/receive positive channel 0 (AIO). |
| 2 | TR0N | bidirectional | Gigabit Ethernet transmit/receive negative channel 0 (AIO). |
| 3 | VDD25A | power_in | +2.5V analog supply input for Gigabit Ethernet PHY. |
| 4 | TR1P | bidirectional | Gigabit Ethernet transmit/receive positive channel 1 (AIO). |
| 5 | TR1N | bidirectional | Gigabit Ethernet transmit/receive negative channel 1 (AIO). |
| 6 | VDD25A | power_in | +2.5V analog supply input for Gigabit Ethernet PHY. |
| 7 | TR2P | bidirectional | Gigabit Ethernet transmit/receive positive channel 2 (AIO). |
| 8 | TR2N | bidirectional | Gigabit Ethernet transmit/receive negative channel 2 (AIO). |
| 9 | VDD25A | power_in | +2.5V analog supply input for Gigabit Ethernet PHY. |
| 10 | TR3P | bidirectional | Gigabit Ethernet transmit/receive positive channel 3 (AIO). |
| 11 | TR3N | bidirectional | Gigabit Ethernet transmit/receive negative channel 3 (AIO). |
| 12 | VDD25A | power_in | +2.5V analog supply input for Gigabit Ethernet PHY. |
| 13 | VDDVARIO | power_in | +1.8V to +3.3V variable I/O supply. |
| 14 | TDI | input | JTAG test data input (VIS buffer). |
| 15 | TDO | output | JTAG test data output (O12 buffer). |
| 16 | TCK/GPIO0 | bidirectional | JTAG test clock, alternate function GPIO0. Max clock is half the system clock. |
| 17 | TMS | input | JTAG test mode select (VIS buffer). |
| 18 | VDD12_SW_OUT | power_out | +1.2V output voltage from integrated switching regulator. |
| 19 | VDD_SW_IN | power_in | +3.3V input voltage for the integrated switching regulator. |
| 20 | VDD12_SW_FB | passive | Feedback pin for integrated switching regulator. Tie to VDD_SW_IN to disable the switcher. |
| 21 | EECS/GPIO1 | output | External EEPROM chip select output (O12). Alternate function GPIO1. |
| 22 | EEDI/GPIO2 | input | External EEPROM data input (driven by EEPROM DO). Alternate function GPIO2. |
| 23 | EEDO/GPIO3 | output | External EEPROM data output driving EEPROM DI (O12). Alternate function GPIO3. |
| 24 | EECLK/GPIO4 | output | External EEPROM clock output (O12). Alternate function GPIO4. |
| 25 | VDDVARIO | power_in | +1.8V to +3.3V variable I/O supply. |
| 26 | VDD12CORE | power_in | +1.2V digital core power supply input. |
| 27 | VBUS_DET | input | Detects state of upstream USB bus power (VIS with pull-down). For bus-powered operation tie to VDD33A. |
| 28 | SUSPEND_N/GPIO5 | output | Asserted when device is in a suspend state (O12). May control an external switcher. Alternate function GPIO5. |
| 29 | CONNECT/GPIO6 | output | USB CONNECT output - asserts when device is attempting to attach to USB host (O12). Alternate function GPIO6. |
| 30 | HSIC_SEL | input | HSIC select: tie to VDD to enable HSIC interface, otherwise USB 2.0 interface is enabled. Static signal, do not change at runtime. |
| 31 | LED0/GPIO7 | output | Indicator LED0 (OD12), configurable for link/activity/duplex/collision. Alternate function GPIO7. |
| 32 | PME_MODE/GPIO8 | input | PME mode selection input when PME mode is active (VIS). Alternate function GPIO8. |
| 33 | VDD12A | power_in | +1.2V analog supply input for USB PLL/AFE. |
| 34 | VDD12HSIC | power_in | +1.2V HSIC power supply input. |
| 35 | STROBE | bidirectional | HSIC bi-directional data strobe signal per HSIC Electrical Specification. |
| 36 | USB_DP | bidirectional | Hi-Speed USB 2.0 D+ data line (AIO). |
| 37 | USB_DM | bidirectional | Hi-Speed USB 2.0 D- data line (AIO). |
| 38 | DATA | bidirectional | HSIC bi-directional DDR data signal, synchronous to STROBE. |
| 39 | PME_N | output | Active-low PME signal output (O8/OD8), asserted during PME operation. |
| 40 | TEST | input | Test pin, for internal purposes only. Must be tied to ground for proper operation. |
| 41 | RESET_N/PME_CLEAR | input | Active-low system reset (VIS). Also serves as PME clear input when PME mode is active. Pull up to VDD if unused. |
| 42 | VDDVARIO | power_in | +1.8V to +3.3V variable I/O supply. |
| 43 | USBRBIAS | passive | USB HS bias reference. Connect to external 12kΩ 1.0% resistor to ground to set HS transmit current and on-chip termination. |
| 44 | VDD33A | power_in | +3.3V analog supply for USB 2.0 AFE. |
| 45 | VDDVARIO | power_in | +1.8V to +3.3V variable I/O supply. |
| 46 | XI | input | External 25 MHz crystal input. May also be driven by a single-ended clock oscillator (leave XO open). |
| 47 | XO | output | External 25 MHz crystal output. Leave unconnected if XI is driven by an external oscillator. |
| 48 | VDD12CORE | power_in | +1.2V digital core power supply input. |
| 49 | LED1/GPIO9 | output | Indicator LED1 (OD12), configurable for link/activity/duplex/collision. Alternate function GPIO9. |
| 50 | LED2/GPIO10 | output | Indicator LED2 (OD12), configurable for link/activity/duplex/collision. Alternate function GPIO10. |
| 51 | LED3/GPIO11 | output | Indicator LED3 (OD12), configurable for link/activity/duplex/collision. Alternate function GPIO11. |
| 52 | VDD12A | power_in | +1.2V analog supply input for USB PLL/AFE. |
| 53 | VDD25_REG_OUT | power_out | +2.5V output from integrated LDO used to supply Gigabit Ethernet PHY AFE. |
| 54 | VDD33_REG_IN | power_in | +3.3V input supply to integrated LDO. |
| 55 | REF_REXT | passive | External PHY reference resistor. Connect to external 2kΩ 1.0% resistor to ground. |
| 56 | REF_FILT | passive | External PHY reference filter. Connect to external 1µF capacitor to ground. |
| 57 | VSS | power_in | Exposed thermal pad. Common ground; must be connected to ground for proper operation and thermal performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-56-EP(8x8) |
| Category | Interface |
| Pins | 57 |
Ordering variants
Same part, different packaging or reel option.
LAN7850T-ILAN7850T-I/YZX
CAD (KiCad official)
- Symbol:
LAN7850T-I - Footprint:
Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm - 3D model: QFN-56-EP(8x8) (KiCad packages3D, STEP)
- 3D model files:
lan7850t-i-etched.step/lan7850t-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lan7850t-i.step/lan7850t-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (277 pp, sha256
41b2cc2942c4219b, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).