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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

LAN7431

Microchip Tech · Ethernet Controllers · QFN-72-EP(10x10)

LAN7431 from Microchip Tech, in a QFN-72-EP(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AVDDH_1	power_in	2.5V or 3.3V power for analog IO; provides power for bandgap reference and crystal oscillator amplifier.
2	AVDDL_1	power_in	1.2V power for analog core.
3	VDDVARIO_B	power_in	1.8V to 3.3V variable supply for RGMII and MII related IOs.
4	TXD3	output	Transmit data output; MAC transmits data to external Ethernet PHY using RGMII signals.
5	TXD2	output	Transmit data output; MAC transmits data to external Ethernet PHY using RGMII signals.
6	TXD1	output	Transmit data output; MAC transmits data to external Ethernet PHY using RGMII signals.
7	VDDVARIO_B	power_in	1.8V to 3.3V variable supply for RGMII and MII related IOs.
8	TXD0	output	Transmit data output; MAC transmits data to external Ethernet PHY using RGMII signals.
9	TX_ER/MII_EN	output	Indicates transmit error condition in RGMII/MII mode or serves as MII mode configuration strap (pulled high selects MII, low/float selects RGMII).
10	TX_CTL/TX_EN	output	Indicates transmit data enable (TXEN) and transmit error (TXER) functions in RGMII or transmit enable in MII mode.
11	TXC/TX_CLK	output	Transmit clock output used to latch data into external Ethernet PHY (125MHz for 1000BASE-T, 25MHz for 100BASE-TX, 2.5MHz for 10BASE-T).
12	VDDVARIO_B	power_in	1.8V to 3.3V variable supply for RGMII and MII related IOs.
13	RXC/RX_CLK	input	Receive clock input used to transfer data from external Ethernet PHY to MAC (125MHz for 1000BASE-T, 25MHz for 100BASE-TX, 2.5MHz for 10BASE-T).
14	RX_CTL/RX_DV	input	Indicates receive data valid (RXDV) and receive error (RXER) functions in RGMII or receive data valid in MII mode.
15	RXD0	input	Receive data input from external Ethernet PHY in RGMII/MII mode.
16	RXD1	input	Receive data input from external Ethernet PHY in RGMII/MII mode.
17	RXD2	input	Receive data input from external Ethernet PHY in RGMII/MII mode.
18	RXD3	input	Receive data input from external Ethernet PHY in RGMII/MII mode.
19	VDDVARIO_B	power_in	1.8V to 3.3V variable supply for RGMII and MII related IOs.
20	CLK125/RX_ER	input	125MHz clock input from external Ethernet PHY used to generate RGMII TX clock or receive error indicator in MII mode.
21	REFCLK_25/GPIO11	output	25MHz reference clock output to external Ethernet PHY or programmable general purpose I/O.
22	COL/GPIO10	input	Collision detect input from external Ethernet PHY (half-duplex mode only) or programmable general purpose I/O.
23	CRS	input	Carrier sense input indicating detection of carrier by external Ethernet PHY (half-duplex mode only).
24	VDD12CORE	power_in	1.2V digital core power supply.
25	VP	power_in	1.2V PCIe PHY analog and digital power supply.
26	GD_1	power_in	PCIe ground connection.
27	PCIE_RX_P	input	PCIe serial data input positive for 2.5 GT/s differential link.
28	PCIE_RX_M	input	PCIe serial data input negative for 2.5 GT/s differential link.
29	GD_2	power_in	PCIe ground connection.
30	PCIE_TX_P	output	PCIe serial data output positive for 2.5 GT/s differential link requiring 100nF to 200nF series capacitor.
31	VPTX	power_in	1.2V PCIe PHY transmit power supply.
32	PCIE_TX_M	output	PCIe serial data output negative for 2.5 GT/s differential link requiring 100nF to 200nF series capacitor.
33	GD_3	power_in	PCIe ground connection.
34	VPH	power_in	2.5V PCIe PHY power supply.
35	RESREF	passive	External reference resistor connection; should be connected to ground through 200 ohm 1% 100 ppm/C resistor for PHY termination impedance calibration.
36	PCIE_CLK_P	input	PCIe differential reference clock input positive receiving 100MHz differential clock input.
37	PCIE_CLK_M	input	PCIe differential reference clock input negative receiving 100MHz differential clock input.
38	VDD25_REG_OUT	power_out	2.5V output supply from integrated LDO regulator used to supply power to PCIe PHY and Ethernet PHY.
39	VDD_REG_IN	power_in	3.3V input supply to integrated LDO regulator (if set to 2.5V shall be externally connected to VDD25_REG_OUT).
40	DUPLEX	input	Duplex mode input from external Ethernet PHY; when set indicates full-duplex mode or should be tied to VDDVARIO if PHY lacks duplex output.
41	PHY_INT_N	input	Interrupt input from external Ethernet PHY.
42	PHY_RESET_N	output	Reset output to external Ethernet PHY.
43	VDDVARIO	power_in	1.8V to 3.3V variable supply for general IOs.
44	RESET_N	input	System reset input active low; must be pulled up to VDDVARIO if unused.
45	TEST	input	Test mode enable input; must be connected to ground for proper functional operation.
46	VDD12CORE	power_in	1.2V digital core power supply.
47	GPIO9/TCK	input	Programmable general purpose I/O or JTAG test clock input (maximum operating frequency is half of system clock).
48	VDDVARIO	power_in	1.8V to 3.3V variable supply for general IOs.
49	GPIO8/TDI	input	Programmable general purpose I/O or JTAG data input.
50	GPIO7/TMS	input	Programmable general purpose I/O or JTAG test mode select input.
51	VDD12_SW_OUT	power_out	1.2V output voltage from integrated switching regulator.
52	VDD_SW_IN	power_in	1.8V to 3.3V input voltage for integrated switching regulator.
53	VDD12_SW_FB	passive	Feedback pin for integrated switching regulator; tie to VDD_SW_IN to disable switching regulator.
54	GPIO6/TDO	output	Programmable general purpose I/O or JTAG test data output.
55	GPIO5	bidirectional	Programmable general purpose I/O configurable as push-pull output, open-drain output, or Schmitt-triggered input with pull-up; pull-up only enabled when set as GPIO.
56	GPIO4	bidirectional	Programmable general purpose I/O configurable as push-pull output, open-drain output, or Schmitt-triggered input with pull-up; pull-up only enabled when set as GPIO.
57	VAUX_DET/GPIO3	input	Auxiliary voltage detection input with internal pull-down indicating PME from D3cold support when tied to auxiliary voltage (3.3V) or programmable GPIO (if alternate usage enabled pull-down is disabled).
58	EECLK/GPIO2/ADV_PM_DISABLE	output	EEPROM clock output with internal pull-down during reset or advanced power management disable configuration strap (pulled high disables L1 PM substates) or programmable GPIO.
59	EEDIO/GPIO1	bidirectional	EEPROM data input/output bidirectional pin with internal pull-down providing low during reset or programmable GPIO.
60	EECS/GPIO0	output	EEPROM chip select output with internal pull-down during reset or programmable GPIO.
61	VDDVARIO	power_in	1.8V to 3.3V variable supply for general IOs.
62	VDD12CORE	power_in	1.2V digital core power supply.
63	MDIO	bidirectional	Management interface data input/output for external Ethernet PHY with internal pull-up; external pull-up required to ensure IDLE state is logic one for MII management interface.
64	MDC	output	Management interface clock output to external Ethernet PHY.
65	VDD_OTP	power_in	3.3V supply for OTP charge pump and PCIe I/Os (CLKREQ#, WAKE#, PERST#).
66	CLKREQ#	tri_state	Clock request input/open-drain output used for PCIe link clock power management and L1 power management substate control.
67	WAKE#	tri_state	Wake signal input/open-drain output driven low when device detects wakeup or used for OBFF events in OBFF mode.
68	PERST#	input	Power and clock good indication input indicating that both PCIe power and reference clock are available.
69	AVDD12	power_in	1.2V power for PLL/DLL.
70	XO	output	25MHz crystal output when using crystal oscillator or unconnected when using external oscillator/reference clock source.
71	XI	input	25MHz crystal input when using crystal oscillator or input from 3.3V oscillator/external reference clock source with tolerance ±50ppm.
72	ISET	passive	External bias resistor connection; should be connected to ground through 6.04K 1% resistor as external PHY bias reference.
73	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-72-EP(10x10)
Category	Interface
Pins	73

CAD (KiCad official)

Symbol: LAN7431
Footprint: Package_DFN_QFN:QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm
3D model: QFN-72-EP(10x10), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: lan7431-etched.step / lan7431-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lan7431.step / lan7431.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (77 pp, sha256 ad01b0713999a060, retrieved 2026-10-01, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF