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LAN7430-I

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Microchip Tech Ethernet ICs, QFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icslan7430-ifactory-2.0.0extractor-text

Verified LAN7430-I

by Ray · last 7 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

7 Nov 2026RayPublished by the parts factory: tier mfr, 49 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: LAN7430-I · QFN-48-EP(7x7) · 49 pins
  • ✓copper: 49 copper pads, none touching another net
  • ✓datasheet: all 49 pin names found in the 77-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-e9cunqkv/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 49 pins = 49 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 49 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ lan7430-i.kicad_sym✓ lan7430-i.kicad_mod✓ lan7430-i.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2d ago
viewers lan7430-i: viewers · Ray 2d ago
lan7430-i-etched.glb Publish 0.1.0 · Ray 2d ago
lan7430-i-etched.step lan7430-i: factory component page (tier=mfr) · Ray 2d ago
lan7430-i-hero.glb lan7430-i: hero GLB from the etched model (keeps the MPN mark) · Ray 2d ago
lan7430-i-hero.overlay.json Publish 0.1.0 · Ray 2d ago
lan7430-i.glb Publish 0.1.0 · Ray 2d ago
lan7430-i.kicad_mod Publish 0.1.0 · Ray 2d ago
lan7430-i.kicad_sym Publish 0.1.0 · Ray 2d ago
lan7430-i.lbr Publish 0.1.0 · Ray 2d ago
lan7430-i.step Publish 0.1.0 · Ray 2d ago
package.json Publish 0.1.0 · Ray 2d ago
page.json Set visibility: public · Ray 2d ago
README.md Publish 0.1.0 · Ray 2d ago
verification.json Verified: Published by the parts factory: tier mfr, 49 pins · Ray 2d ago

LAN7430-I

Microchip Tech · Ethernet ICs · QFN-48-EP(7x7)

LAN7430-I from Microchip Tech, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVDDH_1 power_in 2.5V or 3.3V analog I/O supply powering the Gigabit PHY transmitter, bandgap reference and crystal oscillator amplifier.
2 TXRXP_A bidirectional Media Dependent Interface[0] positive differential signal (BI_DA+ in MDI, BI_DB+ in MDI-X for 1000BT; TX+/RX+ for 10/100).
3 TXRXM_A bidirectional Media Dependent Interface[0] negative differential signal (BI_DA- in MDI, BI_DB- in MDI-X for 1000BT; TX-/RX- for 10/100).
4 AVDDL_1 power_in 1.2V power for the Ethernet PHY analog core.
5 TXRXP_B bidirectional Media Dependent Interface[1] positive differential signal (BI_DB+ in MDI, BI_DA+ in MDI-X for 1000BT; RX+/TX+ for 10/100).
6 TXRXM_B bidirectional Media Dependent Interface[1] negative differential signal (BI_DB- in MDI, BI_DA- in MDI-X for 1000BT; RX-/TX- for 10/100).
7 TXRXP_C bidirectional Media Dependent Interface[2] positive differential signal (BI_DC+ in MDI, BI_DD+ in MDI-X for 1000BT); not used in 10/100 modes.
8 TXRXM_C bidirectional Media Dependent Interface[2] negative differential signal (BI_DC- in MDI, BI_DD- in MDI-X for 1000BT); not used in 10/100 modes.
9 AVDDL_2 power_in Additional 1.2V power pin for the Ethernet PHY analog core.
10 TXRXP_D bidirectional Media Dependent Interface[3] positive differential signal (BI_DD+ in MDI, BI_DC+ in MDI-X for 1000BT); not used in 10/100 modes.
11 TXRXM_D bidirectional Media Dependent Interface[3] negative differential signal (BI_DD- in MDI, BI_DC- in MDI-X for 1000BT); not used in 10/100 modes.
12 AVDDH_2 power_in 2.5V or 3.3V analog I/O power for the Gigabit PHY transmitter.
13 VDD12CORE power_in 1.2V digital core power input.
14 VP power_in 1.2V PCIe PHY analog and digital power.
15 GD_1 power_in PCIe ground.
16 PCIE_RX_P input PCIe serial data input positive, a differential receive link running at 2.5 GT/s.
17 PCIE_RX_M input PCIe serial data input negative, a differential receive link running at 2.5 GT/s.
18 GD_2 power_in PCIe ground.
19 PCIE_TX_P output PCIe serial data output positive at 2.5 GT/s; a 100nF to 200nF series capacitor is required.
20 VPTX power_in 1.2V PCIe PHY transmit power.
21 PCIE_TX_M output PCIe serial data output negative at 2.5 GT/s; a 100nF to 200nF series capacitor is required.
22 GD_3 power_in PCIe ground.
23 VPH power_in 2.5V PCIe PHY power.
24 RESREF passive External reference resistor pin, to be connected to ground through a 200 ohm 1% 100 ppm/°C resistor.
25 PCIE_CLK_P input PCIe differential reference clock input positive, receiving a 100 MHz differential clock.
26 PCIE_CLK_M input PCIe differential reference clock input negative, receiving a 100 MHz differential clock.
27 VDD25_REG_OUT power_out 2.5V output from the integrated LDO supplying the PCIe PHY and optionally the Gigabit Ethernet PHY AFE; needs a 1.0uF 0.1-ohm ESR capacitor.
28 VDD_REG_IN power_in 3.3V input supply to the integrated LDO; if set to 2.5V it must be connected externally to VDD25_REG_OUT.
29 RESET_N input Active-low system reset; must be pulled up to VDDVARIO if unused.
30 TEST input Enables test modes (internal pull-down); must be connected to ground for proper functional operation.
31 VDD12CORE power_in 1.2V digital core power input.
32 VDD12_SW_OUT power_out 1.2V unfiltered output from the integrated switching regulator, used with a 3.3uH inductor to the 1.2V supply.
33 VDD_SW_IN power_in 1.8V to 3.3V input voltage for the switching regulator.
34 VDD12_SW_FB input Feedback pin for the integrated switching regulator; tie to VDD_SW_IN to disable the regulator.
35 VAUX_DET/GPIO3/LED3/TCK bidirectional Auxiliary voltage detect (internal pull-down; tie to 3.3V aux to indicate PME from D3cold support) shared with GPIO3, LED3 and JTAG TCK.
36 EECLK/GPIO2/LED2/TMS/ADV_PM_DISABLE bidirectional EEPROM clock output shared with GPIO2, LED2, JTAG TMS and the ADV_PM_DISABLE configuration strap latched at reset.
37 EEDIO/GPIO1/LED1/TDO bidirectional Bidirectional EEPROM data pin (internal pull-down) shared with GPIO1, LED1 and JTAG TDO.
38 EECS/GPIO0/LED0/TDI bidirectional EEPROM chip-select output (internal pull-down holds low during reset) shared with GPIO0, LED0 and JTAG TDI.
39 VDDVARIO power_in 1.8V to 3.3V variable supply for IOs.
40 VDD12CORE power_in 1.2V digital core power input.
41 VDD_OTP power_in 3.3V supply to the OTP charge pump, also the 3.3V supply for PCIe I/Os (CLKREQ#, WAKE#, PERST#).
42 CLKREQ# bidirectional Clock request used to power manage the link clock and for L1 PM sub-state control; Schmitt input / 4 mA open-drain output.
43 WAKE# bidirectional Driven low when the device detects a wakeup; used as an input for OBFF events in OBFF mode; Schmitt input / 4 mA open-drain output.
44 PERST# input PCIe reset input indicating both PCIe power and clock are available.
45 AVDD12 power_in 1.2V power for the PLL/DLL.
46 XO output Crystal output connected to one lead of the 25MHz crystal; not connected when an oscillator or external clock is used.
47 XI input Crystal or oscillator input: one lead of the 25MHz crystal, or the clock source input for a 3.3V oscillator or external clock with ±50ppm tolerance.
48 ISET passive External PHY bias resistor pin, to be connected to ground through a 6.04K 1% resistor.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-48-EP(7x7)
Category Interface ICs
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (VDD_SW_IN) VDD_SW_IN 1.62 3.63 V 48
Supply Voltage (VDDVARIO, VDDVARIO_B) VDDVARIO 1.62 3.63 V 48
Supply Voltage (VDD_REG_IN, VDD_OTP) VDD_REG_IN 2.97 3.63 V 48
+2.5/3.3 V Ethernet PHY Analog Supply Voltage (AVDDH_1, AVDDH_2) AVDDH_1, AVDDH_2 2.33 2.75 V 2.5 V option, Note 7-2 48
+2.5/3.3 V Ethernet PHY Analog Supply Voltage (AVDDH_1, AVDDH_2) AVDDH_1, AVDDH_2 2.97 3.63 V 3.3 V option 48
+2.5 V PCIe PHY Analog Supply Voltage (VPH) VPH 2.33 2.75 V 48
+1.2 V PCIe PHY Analog Supply Voltage (VPTX, VP) VPTX, VP 1.12 1.32 V 48
+1.2 V Ethernet PHY Analog Supply Voltage (AVDD12, AVDDL_1, AVDDL_2) AVDD12, AVDDL_1, AVDDL_2 1.14 1.32 V 48
Digital Supply Voltage (VDD12CORE) VDD12CORE 1.14 1.32 V 48
Ambient Operating Temperature in Still Air TA -40 85 °C industrial version (Note 7-3) 48
Positive voltage on input signal pins, with respect to ground (operating) 3.63 V 48
Negative voltage on input signal pins, with respect to ground (operating) -0.3 V 48
Supply Voltage (VDDVARIO, VDDVARIO_B, VDD_SW_IN, VDD_REG_IN, VDD_OTP) VDDVARIO, VDDVARIO_B, VDD_SW_IN, VDD_REG_IN, VDD_OTP -0.5 4.6 V Note 7-1 48
+2.5/3.3 V Analog Supply Voltage (AVDDH_1, AVDDH_2) AVDDH_1, AVDDH_2 -0.5 4.6 V Note 7-1 48
+2.5 V Analog Supply Voltage (VPH) VPH -0.5 3.2 V Note 7-1 48
+1.2 V Analog Supply Voltage (AVDD12, AVDDL_1, AVDDL_2, VPTX, VP) AVDD12, AVDDL_1, AVDDL_2, VPTX, VP -0.5 1.5 V Note 7-1 48
+1.2 V Digital Supply Voltage (VDD12CORE) VDD12CORE -0.5 1.5 V Note 7-1 48
Positive voltage on input signal pins, with respect to ground 4.6 V 48
Negative voltage on input signal pins, with respect to ground -0.5 V 48
Storage Temperature -65 150 °C 48
HBM ESD Performance -2 2 kV HBM 48
Junction-to-ambient thermal resistance (JA), 48-SQFN JA 26.4 °C/W Velocity 0 m/s, multi-layer 2S2P PCB 49
Junction-to-ambient thermal resistance (JA), 48-SQFN JA 23.1 °C/W Velocity 1 m/s, multi-layer 2S2P PCB 49
Junction-to-top thermal parameter (JT), 48-SQFN JT 0.2 °C/W Velocity 0 m/s 49
Junction-to-top thermal parameter (JT), 48-SQFN JT 0.3 °C/W Velocity 1 m/s 49
Junction-to-case thermal resistance (JC), 48-SQFN JC 1.8 °C/W N/A 49
Non-variable I/O Low Input Level VIL 0.8 V 52
Non-variable I/O High Input Level VIH 2 V 52
Non-variable I/O Schmitt Trigger Hysteresis (VIHT - VILT) VHYS 100 127 245 mV Schmitt trigger 52
Non-variable I/O Input Leakage (VIN = VSS or VDD_OTP) IIH -10 10 µA VIN = VSS or VDD_OTP 52
Non-variable I/O Input Capacitance CIN 2 3 pF 52
OD4 Type Buffer Low Output Level VOL 0.2 V IOL = -4 mA 52
ICLK Type Input Buffer Low Input Level VIL 0.5 V 52
ICLK Type Input Buffer High Input Level VIH 2 V 52
ICLK Type Input Buffer Input Leakage IIH -10 10 µA 52
VO8 Type Buffer Low Output Level VOL 0.4 V IOL = -8 mA 53
VO12 Type Buffer Low Output Level VOL 0.4 V IOL = -12 mA 53
RGMII_O Type Buffer Low Output Level VOL 0.4 V IOL = -6 mA 54
1000BASE-T Peak Differential Output Voltage VOP 670 820 mV IEEE 802.3 clause 40.6.1.2.1 54
1000BASE-T Signal Amplitude Symmetry VSS 1 % IEEE 802.3 clause 40.6.1.2.1 54
100BASE-TX Peak Differential Output Voltage VOUT 0.95 1.05 V ANSI X3.263 clause 9.1.2.2 55
100BASE-TX Signal Rise and Fall Time TRF 3 5 nS ANSI X3.263 clause 9.1.6 55
100BASE-TX Duty Cycle Distortion DCD -0.25 0.25 nS Offset from 16nS pulse width at 50% of pulse peak 55
100BASE-TX Output Jitter 0.7 1.4 nS Peak to peak, measured differentially 55
10BASE-T Transmitter Peak Differential Output Voltage VOUT 2.2 2.5 2.8 V 10BASE-T, IEEE 802.3 clause 14.3.1.2.1 55
10BASE-Te Transmitter Peak Differential Output Voltage VOUT 1.54 1.96 V 10BASE-Te 55
10BASE-T Output Jitter 1.8 3.5 nS IEEE 802.3 clause 14.3.1.2.3 55
10BASE-T Signal Rise and Fall Time TRF 25 nS 55
10BASE-T Receiver Differential Squelch Threshold VDS 300 400 mV IEEE 802.3 clause 14.3.1.3.2 55
Power supply turn on time tpon 50 ms 57
Power supply turn off time tpoff 500 ms 57
RESET_N input assertion time trstia 1 µs 58
Configuration strap setup before RESET_N deassertion tcss 200 ns 58
Frequency Tolerance @ 25°C Ftol -50 50 PPM Crystal, Note 7-44 68
Frequency Stability Over Temp Ftemp -50 50 PPM Crystal, Note 7-44 68
Shunt Capacitance CO 6 pF Crystal 68
Load Capacitance CL 25 pF Crystal 68
Drive Level PW 100 µW Crystal 68
Equivalent Series Resistance R1 50 Ohm Crystal 68

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing ppa • Energy Efficient Ethernet (EEE) Support with Low-Power Idle (LPI) Mode and Clock Stoppage for 100BASE-TX/ 35

CAD (KiCad official)

  • Symbol: LAN7430-I
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: lan7430-i-etched.step / lan7430-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lan7430-i.step / lan7430-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (77 pp, sha256 3322865bd323f04f, retrieved 2026-11-07, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF