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L99DZ100GTR

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STMicroelectronics Power Management - Specialized, LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)l99dz100gtrfactory-2.0.0extractor-text
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L99DZ100GTR

STMicroelectronics · Power Management - Specialized · LQFP-64(10x10)

L99DZ100GTR from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 WU input Wake-up input pin for static or cyclic monitoring of external contacts; supports -0.3 to +28V normal, -0.3 to +40V load dump.
2 CP2M passive Charge pump capacitor 2 negative side connection for external capacitor.
3 CP2P passive Charge pump capacitor 2 positive side connection for external capacitor.
4 CP output Charge pump output supplying high voltage to gate drivers; maximum +40V, minimum VS-0.3V.
5 CP1P passive Charge pump capacitor 1 positive side connection for external capacitor; VS-0.3 to VS+14V.
6 CP1M passive Charge pump capacitor 1 negative side connection for external capacitor; -0.3 to VS+0.3V.
7 GHheater output Gate driver output for external N-Channel MOSFET in high-side heater configuration; VSheater-0.3 to VSheater+13V or VCP+0.3V.
8 SHheater passive Source connection point of high-side MOSFET for heater; -0.3 to 40V or -0.3 to VS+0.3V.
9 OUT14 output High-side driver output for LED control with maximum output current ±1.25A.
10 OUT13 output High-side driver output for LED control with maximum output current ±1.25A.
11 OUT12 output High-side driver output for LED control with maximum output current ±1.25A.
12 OUT9 output High-side driver output for LED control with maximum output current ±1.25A.
13 OUT10 output High-side driver output for LED control; can be switched via ECON bit for electro-chrome control with higher priority; ±1.25A maximum.
14 OUT11 output High-side driver output for LED control with maximum output current ±1.25A.
15 LS1_FSO output Fail-safe low-side switch output (active low) for gate pull-down of external high-side MOSFET.
16 LS2_FSO output Fail-safe low-side switch output (active low) for gate pull-down of external high-side MOSFET.
17 VS power_in Power supply input for power stage outputs; 6.5 to 28V normal, -0.3 to +40V load dump; requires ceramic capacitor to GND and external reverse battery protection.
18 VS power_in Power supply input for power stage outputs, second pin for current distribution capability; all VS pins must be connected externally for full output current.
19 OUT7 output High-side driver output for LED or 10W bulb with programmable Rdson; maximum output current ±5A.
20 OUT6 output Half-bridge output combining high-side and low-side switches with internal parasitic reverse diodes; ±5A maximum current.
21 OUT1 output Half-bridge output combining high-side and low-side switches with internal parasitic reverse diodes; ±5A maximum current.
22 OUT2 output Half-bridge output combining high-side and low-side switches with internal parasitic reverse diodes; ±5A maximum current.
23 OUT5 output Half-bridge output combining high-side and low-side switches with internal parasitic reverse diodes; ±10A maximum current.
24 OUT5 output Second pin connection to OUT5 for current distribution capability.
25 VSREG power_in Power supply input for internal voltage regulators V1, V2 and outputs OUT15, OUT_HS; requires ceramic capacitor to GND, electrolytic backup capacitor, and external reverse battery protection with diode.
26 OUT_HS output High-side driver output for LED control or external contact supply with maximum output current ±1.25A.
27 OUT4 output Half-bridge output combining high-side and low-side switches with internal parasitic reverse diodes; ±10A maximum current.
28 OUT4 output Second pin connection to OUT4 for current distribution capability.
29 OUT3 output Half-bridge output combining high-side and low-side switches with internal parasitic reverse diodes; ±10A maximum current.
30 VS power_in Power supply input for power stage outputs, third pin for current distribution capability.
31 OUT15 output High-side driver output for LED control with maximum output current ±1.25A.
32 PGND power_in Power ground connection for all output power stages; must be connected externally for complete power return path.
33 OUT8 output High-side driver output for LED control or 5W bulb with programmable Rdson; maximum output current ±2.5A.
34 ECDR output Gate driver output for external N-Channel MOSFET control in electro-chromic glass mode.
35 SGND power_in Signal ground connection for logic and analog circuits; reference for ADC and current monitor measurements.
36 CM output Current monitor output providing scaled image of high-side driver current based on CM_SEL_x register selection.
37 ECV input Voltage monitor input for electro-chromic glass control with integrated low-side discharge switch.
38 CLK input SPI serial clock input; operates up to 4MHz with CPOL=0, CPHA=0 protocol.
39 DO tri_state SPI serial data output (push-pull); presents global error flag when CSN=low; high impedance when CSN=high.
40 DI input SPI serial data input; data sampled at rising edge of CLK and shifted into 32-bit shift register.
41 CSN input SPI chip select input (active low); initiates communication frame; output high-Z if CSN low for >tCSNfail.
42 TxD_L input LIN transmit data input; multi-level input range -0.3 to 40V.
43 RxD_L/NINT output LIN receive data output or interrupt output (push-pull); indicates local/remote wake-up events.
44 TxD_C input CAN transmit data input; multi-level input range -0.3 to 40V.
45 RxD_C/NINT output CAN receive data output or interrupt output (push-pull); indicates local/remote wake-up events.
46 DIR1 input Direct drive input 1 for internal driver control; logic level input -0.3 to V1+0.3V.
47 PWMH input PWM input for H-bridge gate driver control; logic level input -0.3 to V1+0.3V.
48 DIRH input Direction input for H-bridge external MOSFET driver control; logic level input -0.3 to V1+0.3V.
49 DIR2 input Direct drive input 2 for internal driver control; logic level input -0.3 to V1+0.3V.
50 NRESET output Reset output to microcontroller (low-side switch with internal pull-up to 5V_1); reset state = LOW.
51 5V_1 power_out Voltage regulator 1 output (5V nominal) supplying microcontroller and CAN transceiver.
52 CAN Supply power_in CAN supply input for external CAN transceiver; allows external CAN supply from V1 or V2 regulator; -0.3 to +5.25V.
53 NINT output Interrupt output (low-active, push-pull); indicates VSREG early warning in active mode or wake-up from V1_standby.
54 CAN_L bidirectional CAN low differential bus line; bidirectional I/O range -27 to +40V; differential voltage with CAN_H from -5 to +10V.
55 CAN_H bidirectional CAN high differential bus line; bidirectional I/O range -27 to +40V; differential voltage with CAN_L from -5 to +10V.
56 Debug input Debug input (high-active) to deactivate window watchdog; logic level input range -0.3 to V1+0.3V.
57 LIN bidirectional LIN bus transceiver line; bidirectional I/O range -20 to +40V; LIN 2.2a compliant.
58 5V_2 power_out Voltage regulator 2 output (5V nominal) supplying external loads (sensors, potentiometers) or CAN transceiver; protected against reverse supply.
59 GL1 output Gate driver output for low-side MOSFET in half-bridge 1; VSxy-0.3 to VSxy+13V or VCP+0.3V.
60 SH1 passive Source connection point for high-side MOSFET in half-bridge 1; -1 to 40V or -0.3 to VS+0.3V.
61 GH1 output Gate driver output for high-side MOSFET in half-bridge 1; VSxy-0.3 to VSxy+13V or VCP+0.3V.
62 GH2 output Gate driver output for high-side MOSFET in half-bridge 2; VSxy-0.3 to VSxy+13V or VCP+0.3V.
63 SH2 passive Source connection point for high-side MOSFET in half-bridge 2; -1 to 40V or -0.3 to VS+0.3V.
64 GL2 output Gate driver output for low-side MOSFET in half-bridge 2; VSxy-0.3 to VSxy+13V or VCP+0.3V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-64(10x10)
Category Power Management (PMIC)
Pins 64

CAD (KiCad official)

  • Symbol: L99DZ100GTR
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: l99dz100gtr-etched.step / l99dz100gtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l99dz100gtr.step / l99dz100gtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (197 pp, sha256 d078940241be0c50, retrieved 2026-09-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF