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L99ASC03GTR

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STMicroelectronics Motor Driver ICs, TQFP-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsl99asc03gtrfactory-2.0.0extractor-text

Verified L99ASC03GTR

by Ray · last 30 Oct 2026 · 1 record · files match
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Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 49 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: L99ASC03GTR · TQFP-48-EP(7x7) · 49 pins
  • ✓copper: 49 copper pads, none touching another net
  • ✓datasheet: all 49 pin names found in the 70-page datasheet
  • ✓distributor: lcsc C2150702, digikey 497-17941-2-ND, mouser 511-L99ASC03GTR
  • ✓family: TQFP-48-1EP_7x7mm_P0.5mm_EP5x5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-eghko6cj/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 49 pins = 49 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 49 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ l99asc03gtr.kicad_sym✓ l99asc03gtr.kicad_mod✓ l99asc03gtr.step
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Ray Publish 0.1.0 12cce65 8d ago

L99ASC03GTR

STMicroelectronics · Motor Driver ICs · TQFP-48-EP(7x7)

L99ASC03GTR from STMicroelectronics, in a TQFP-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SL3 bidirectional Source of external low-side MOSFET 3.
2 CSI+ input Current-sense amplifier positive input.
3 CSI- input Current-sense amplifier negative input.
4 SGND2 power_in Signal ground 2.
5 CSO output Current-sense amplifier output.
6 IL3 input Input of low-side switch 3, one input per gate driver with cross-current protection.
7 IH3 input Input of high-side switch 3, one input per gate driver with cross-current protection.
8 IL2 input Input of low-side switch 2, one input per gate driver with cross-current protection.
9 IH2 input Input of high-side switch 2, one input per gate driver with cross-current protection.
10 IL1 input Input of low-side switch 1, one input per gate driver with cross-current protection.
11 IH1 input Input of high-side switch 1, one input per gate driver with cross-current protection.
12 SGND1 power_in Signal ground 1.
13 SDI input SPI serial data input, latched on the rising edge of SCK.
14 SCK input SPI clock input.
15 SDO output SPI serial data output, shifted out on the falling edge of SCK and high impedance when CSN is high.
16 CSN input SPI chip select not input; communication is active when this input is logically low.
17 BC input Block commutation sync pin.
18 DIS input Disable input that turns off the gate driver outputs.
19 NRES output NReset output, pulled up to VDD by an internal pull-up resistor after a delay tRP (typ. 2 ms).
20 AOUT output Analog multiplexer output for monitoring external supply voltages and internal junction temperature.
21 BEMFOUT output Back EMF output.
22 DOUT output Digital multiplexer output.
23 NINT output Interrupt output.
24 SGND3 power_in Signal ground 3.
25 Reserved unconnected Pin must be kept not connected.
26 AGND power_in Analog ground.
27 VDD power_out Voltage regulator output providing 5 V and a continuous load current up to 200 mA.
28 Reserved unconnected Pin must be kept not connected.
29 INH input Inhibit input for wake-up.
30 VSREG power_in Voltage regulator power supply input; it has to be protected against negative voltages.
31 VS power_in Charge pump power supply input; it has to be protected against negative voltages.
32 CP1- output Charge pump pin for capacitor 1, negative side.
33 CP1+ output Charge pump pin for capacitor 1, positive side.
34 CP2- output Charge pump pin for capacitor 2, negative side.
35 CP2+ output Charge pump pin for capacitor 2, positive side.
36 CP power_out Charge pump output that supplies the gate drivers for full drive of the external MOSFETs.
37 VSMS power_in Motor supply sense pin, robust against negative voltages, used to monitor the external MOSFET supply and as BEMF detection reference.
38 GH1 output Gate of external high-side MOSFET 1.
39 SH1 bidirectional Source of external high-side MOSFET 1.
40 GL1 output Gate of external low-side MOSFET 1.
41 SL1 bidirectional Source of external low-side MOSFET 1.
42 GH2 output Gate of external high-side MOSFET 2.
43 SH2 bidirectional Source of external high-side MOSFET 2.
44 GL2 output Gate of external low-side MOSFET 2.
45 SL2 bidirectional Source of external low-side MOSFET 2.
46 GH3 output Gate of external high-side MOSFET 3.
47 SH3 bidirectional Source of external high-side MOSFET 3.
48 GL3 output Gate of external low-side MOSFET 3.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package TQFP-48-EP(7x7)
Category Power Management ICs
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Voltage regulator power supply voltage VSREG -0.3 40 V 31
Charge pump power supply voltage VS -0.3 40 V 31
Sensed motor supply voltage VSMS -5 40 V -7 V for < 1.5 µs transients 31
Stabilized supply voltage VDD -0.3 6 V 31
Source signal voltage range VSLX, VSHX -5 40 V 31
High Voltage Logic I/O voltage range VINH -0.3 40 V 31
Storage temperature Tstg -55 150 °C 32
Dynamic junction temperature TJ_Peak 160 °C 100hrs over lifetime; according to mission profile 32
Voltage regulator power supply voltage VSREG 6 28 V 31
Charge pump power supply voltage VS 6 28 V 31
Sensed motor supply voltage VSMS 6 28 V 32
Current sense amplifier input voltage range VCSIP, VCSIN -1 1 V 32
Operating junction temperature Tj -40 150 °C 32
Temp. warning threshold 1 TW1 120 135 150 °C TEMPM = X 32
Temp. warning threshold 2 TW2 140 155 170 °C TEMPM = 1 32
Thermal shutdown threshold 2 TSD2 160 175 190 °C TEMPM = X 32
Overvoltage warning threshold VSOVW, VSREGOVW, VSMSOVW 18 20 22 V 33
Overvoltage threshold VSOV, VSREGOV, VSMSOV 28.1 30 32 V 33
Under-voltage threshold VSUV, VSREGUV, VSMSUV 5.2 5.5 5.7 V VS, VSREG, VSMS decreasing 33
Current consumption IS 5 10 mA VS =VSREG =VSMS = 12 V; active mode; open outputs 33
Quiescent current in VBAT stand-by ISREGQ + ISMQ +ISQ 24 38.5 µA VS = VSREG = VSMS = 12 V; VBAT standby (no wakeup); TTest = -40°C to 25°C; open outputs 33
Output voltage VDD 4.865 5 5.1 V Iload = 0 mA to 200 mA; 6 V < Vs < 18 V; -40°C < Tj < 150°C 34
Drop-out Voltage VDP 0.2 0.4 V ILOAD = 50 mA; VSREG = 4.5 V 34
Drop-out Voltage VDP 0.3 0.5 V ILOAD = 100 mA; VSREG = 4.5 V 34
Output current in active mode IDD 200 mA Max. continuous load current 34
Short circuit output current IDDshort 300 600 950 mA Current limitation 34
VDD deactivation time after thermal shutdown tTSD 0.8 1 1.5 s 34
VDD fail threshold VDDFAIL 1.8 2 2.2 V VDD short to ground during startup 34
Drain-source voltage threshold 1 VSCd1 0.4 0.5 0.6 V DSMTH = 00 40
Drain-source voltage threshold 2 VSCd2 0.9 1 1.1 V DSMTH = 01 40
Drain-source voltage threshold 3 VSCd3 1.35 1.5 1.65 V DSMTH = 10 40
Drain-source voltage threshold 4 VSCd4 1.85 2 2.15 V DSMTH = 11 40
VSxOUT voltage ratio VSxOUT 0.106 0.125 0.144 AOUT sinking/ sourcing 2 mA 41
DC gain A20 18.4 19.6 20.4 GCSA = 00 41
DC gain A30 29.4 30 30.6 GCSA = 01 41
DC gain A70 67.9 70 72.1 GCSA = 10 41
DC gain A100 97.5 100 102.5 GCSA = 11 41
Input offset voltage VIO -3.5 3 mV -200 mV < CSI- < 1 V 41
Maximum output overcurrent threshold voltage VoOCMAX 2.35 V OCTH = 11111 41
Comparator threshold of VSMS / 2 comparator VBEMFx -0.13 0.13 V VSMS = 12 V; BEMFMOD = 1; relative to VSMS/2 42
Comparator threshold of GND comparator VBEMFx -0.1 0 0.1 V VSMS = 12 V; BEMFMOD = 0; BEMFSW = 0 42
Input high level Vin H 1.8 5.5 V 42
Threshold for entering Flash Mode, rising voltage VBC,rising 11.4 12.4 13.5 V 42
Threshold for entering Flash Mode, falling voltage VBC,falling 10.9 11.9 13 V 42
Pull up resistor at input DIS, IHx RDIS 50 100 200 k 42
Output low level VBEMFL 0.2 0.4 V ILOAD = 1 mA 42
Current threshold ITH 80 120 µA 43
Pull-down current IPD 30 70 µA VIN = 12 V 43
Output low level VSDOL 0.2 0.4 V ISDO = 1 mA 43
Serial clock frequency fSCK 4.5 MHz 44
CSN falling until SDO valid tCSNQV 100 ns Cout = 50 pF 44
CSN rising until SDO tristate tCSNQT 150 ns Cout = 50 pF 44
SCK falling until SDO valid tSCKQV 90 ns Cout = 50 pF 44
Minimum CSN high time tHCSN 4 µs 44
Thermal resistance to ambient Rth j-amb 33 °C/W IC soldered on 2s2p PCB thermally enhanced 32
Thermal resistance to case Rth j-case 12 °C/W 32

CAD (KiCad official)

  • Symbol: L99ASC03GTR
  • Footprint: Package_QFP:TQFP-48-1EP_7x7mm_P0.5mm_EP5x5mm
  • 3D model: TQFP-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: l99asc03gtr-etched.step / l99asc03gtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l99asc03gtr.step / l99asc03gtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (70 pp, sha256 f86911f3d6459f33, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF