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L9945TR

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STMicroelectronics Power Management - Specialized, TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)l9945trfactory-2.0.0extractor-text

Verified L9945TR

by Ray · last 5 Nov 2026 · 1 record · files match
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5 Nov 2026RayPublished by the parts factory: tier mfr, 64 pinsfiles match
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  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: L9945TR · TQFP-64(10x10) · 64 pins
  • ✓copper: 64 copper pads, none touching another net
  • ✓datasheet: all 64 pin names found in the 151-page datasheet
  • ✓distributor: lcsc C2156048, digikey 497-18911-2-ND, mouser 511-L9945TR
  • ✓family: TQFP-64_10x10mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-u3_5ea4a/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 64 pins = 64 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 64 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ l9945tr.kicad_sym✓ l9945tr.kicad_mod✓ l9945tr.step
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Contents

README

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L9945TR

STMicroelectronics · Power Management - Specialized · TQFP-64(10x10)

L9945TR from STMicroelectronics, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NON1 input Output 1 ON-OFF signal (NPWM signal for H-Bridge 1); digital input with pull-up, active low, 2 kV HBM ESD.
2 NON2 input Output 2 ON-OFF signal (DIR signal for H-Bridge 1); digital input with pull-up, active low, 2 kV HBM ESD.
3 NON3 input Output 3 ON-OFF signal (HIZ signal for H-Bridge 1); digital input with pull-up, active low, 2 kV HBM ESD.
4 NON4 input Output 4 ON-OFF signal; digital input with pull-up, active low, 2 kV HBM ESD.
5 NON5 input Output 5 ON-OFF signal (NPWM signal for H-Bridge 2); digital input with pull-up, active low, 2 kV HBM ESD.
6 NON6 input Output 6 ON-OFF signal (DIR signal for H-Bridge 2); digital input with pull-up, active low, 2 kV HBM ESD.
7 NON7 input Output 7 ON-OFF signal (HIZ signal for H-Bridge 2); digital input with pull-up, active low, 2 kV HBM ESD.
8 NON8 input Output 8 ON-OFF signal; digital input with pull-up, active low, 2 kV HBM ESD.
9 VIO power_in Supply voltage for SDO, must be connected to the same supply as the master SPI device; VIO range -0.3 to 40 V per Table 2.
10 SDO output SPI data out; requires an external pull-down resistor in the 10k to 47k range vs GNDIO.
11 GNDIO power_in Ground for SPI, must be shorted to GNDCP.
12 NRES input Reset input, must be connected to ECU reset; active low with pull-up and 2 kV HBM ESD.
13 NCS input SPI chip select, pull-up, active low.
14 SDI input SPI data in with pull-up.
15 SCK input SPI clock with pull-up.
16 DIS input Disable input, must be connected to the external microcontroller to allow disabling of outputs 1-6; pull-up, active high.
17 DRN8 input FET drain on channel 8; ESD ±4 kV HBM.
18 GNSP8 output NFET gate / PFET source on channel 8; ESD ±4 kV HBM.
19 SNGP8 output NFET source / PFET gate on channel 8; ESD ±4 kV HBM.
20 BATT78 power_in Battery supply for channels 7 and 8; BATTxx range -1 to 60 V per Table 2.
21 SNGP7 output NFET source / PFET gate on channel 7; ESD ±4 kV HBM.
22 GNSP7 output NFET gate / PFET source on channel 7; ESD ±4 kV HBM.
23 DRN7 input FET drain on channel 7; ESD ±4 kV HBM.
24 PGND78 power_in Power ground for channels 7 and 8; ground voltage range -0.3 to 0.3 V per Table 2.
25 PGND56 power_in Power ground for channels 5 and 6; ground voltage range -0.3 to 0.3 V per Table 2.
26 DRN6 input FET drain on channel 6; ESD ±4 kV HBM.
27 GNSP6 output NFET gate / PFET source on channel 6; ESD ±4 kV HBM.
28 SNGP6 output NFET source / PFET gate on channel 6; ESD ±4 kV HBM.
29 BATT56 power_in Battery supply for channels 5 and 6; BATTxx range -1 to 60 V per Table 2.
30 SNGP5 output NFET source / PFET gate on channel 5; ESD ±4 kV HBM.
31 GNSP5 output NFET gate / PFET source on channel 5; ESD ±4 kV HBM.
32 DRN5 input FET drain on channel 5; ESD ±4 kV HBM.
33 RESERVED unconnected Reserved pin; leave floating.
34 RESERVED unconnected Reserved pin; leave floating.
35 VDD5 power_in 5 V input (usually output of external regulator); operating range 4.5 V to 5.5 V.
36 GND power_in Ground; ground voltage range -0.3 to 0.3 V per Table 2.
37 GNDCP power_in Ground for charge pump, must be shorted to GNDIO.
38 VGBHI power_out Charge pump output (battery + 12 V), connected to VPS through a tank capacitor; VGBHI-VPS max 20 V.
39 CH4 bidirectional 2nd node for flying capacitor 2 of the charge pump.
40 CH2 bidirectional 2nd node for flying capacitor 1 of the charge pump.
41 CH3 bidirectional 1st node for flying capacitor 2 of the charge pump.
42 VPS power_in Battery input used to supply the charge pump; static VPS range -1 to 60 V per Table 2.
43 CH1 bidirectional 1st node for flying capacitor 1 of the charge pump.
44 RESERVED input Reserved pin; tie low.
45 NDIS bidirectional Negated disable input/output; can act as a negated disable input or as an interrupt output to the microcontroller when pulled down; pull-down, active low.
46 RESERVED unconnected Reserved pin; leave floating.
47 EN6 input Output 6 enable, used to enable the output driver for safety relevant load control; pull-down, active high.
48 RESERVED unconnected Reserved pin; leave floating.
49 DRN4 input FET drain on channel 4; ESD ±4 kV HBM.
50 GNSP4 output NFET gate / PFET source on channel 4; ESD ±4 kV HBM.
51 SNGP4 output NFET source / PFET gate on channel 4; ESD ±4 kV HBM.
52 BATT34 power_in Battery supply for channels 3 and 4; BATTxx range -1 to 60 V per Table 2.
53 SNGP3 output NFET source / PFET gate on channel 3; ESD ±4 kV HBM.
54 GNSP3 output NFET gate / PFET source on channel 3; ESD ±4 kV HBM.
55 DRN3 input FET drain on channel 3; ESD ±4 kV HBM.
56 PGND34 power_in Power ground for channels 3 and 4; ground voltage range -0.3 to 0.3 V per Table 2.
57 PGND12 power_in Power ground for channels 1 and 2; ground voltage range -0.3 to 0.3 V per Table 2.
58 DRN2 input FET drain on channel 2; ESD ±4 kV HBM.
59 GNSP2 output NFET gate / PFET source on channel 2; ESD ±4 kV HBM.
60 SNGP2 output NFET source / PFET gate on channel 2; ESD ±4 kV HBM.
61 BATT12 power_in Battery supply for channels 1 and 2; BATTxx range -1 to 60 V per Table 2.
62 SNGP1 output NFET source / PFET gate on channel 1; ESD ±4 kV HBM.
63 GNSP1 output NFET gate / PFET source on channel 1; ESD ±4 kV HBM.
64 DRN1 input FET drain on channel 1; ESD ±4 kV HBM.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package TQFP-64(10x10)
Category Power Management (PMIC)
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD5 voltage range VDD5 -0.3 40 V 13
Static VPS voltage range VVPS_sta -1 60 V Ext. HS, Static; Max voltage: VGBHI, VPS = 20 V 13
Dynamic VPS voltage range VVPS_dyn -2 60 V Dynamic; 2 ms test pulse 13
Leakage on pin VPS IPS_leak 0 20 µA POR or NRES active; VPS = [0, 36] V 13
VGBHI voltage range (Ch. Pump) VGBHI -0.3 80 V Max voltage: VGBHI, VPS = 20 V 13
VIO voltage range VVIO -0.3 40 V Supply for SDO 13
SNGPx voltage range VSNGPx -14 60 V Max voltage: GNSPx - SNGPx = 20 V (in all conditions); BATTxx, SNGPx ≥ 0 V (When DSM is used for OC detection) 13
GNSPx voltage range VGNSPx -14 80 V Max voltage: GNSPx - SNGPx = 20 V 13
DRNx voltage range VDRNx -20 60 V 13
BATTxx voltage range VBATTxx -1 60 V Max voltage: BATTxx, SNGPx ≥ 0 V; When DSM is used for OC detection 13
Ground voltage range VGND_PINS -0.3 0.3 V 13
CH1 & CH3 VCH1&3 -0.3 60 V 13
CH2 & CH4 VCH2&4 -0.3 80 V CH2 - VPS = 20 V; CH4 - CH2 = 20 V; VGBHI - CH4 = 20 V 14
Digital HV input voltage range VDIG_IO -0.3 40 V SDO and NDIS have to withstand this voltage also in ON-condition 14
Operating / Lifetime junction temperature Tj_op -40 150 °C Lifetime guaranteed 16
Storage temperature Tstg -40 150 °C -55 °C is allowed for a maximum of 15h 16
Over temperature comparator threshold TOT_OFF 165 190 °C 16
Thermal resistance junction to case Rth_j_c 2.4 °C/W Values are according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board 16
Thermal resistance junction to ambient Rth_j_a 30 °C/W 16
VPS operational supply range VVPS 3.8 36 V Operational 18
VPS load dump VVPS 60 V Load dump (< 500 ms) 18
VPS supply for 15 min VVPS 48 V For 15 min at 45 °C 18
VDD5 supply range VVDD5 4.5 5.5 V Supply for internal digital, analog and SPI (except SDO) Tj = Tj_op 18
VIO supply range VVIO 3 5.5 V Supply for SPI pin SDO Tj = Tj_op 18
VDD5 operating mode current IVDD5_opm 7 35 mA All outputs controlled ON 20
VDD5 current in case of overvoltage IVDD5OV 8 40 mA 5.5 V < VDD5 ≤ 36 V 20
VDD5 UV threshold VVDD5_UV 4.5 4.7 V Undervoltage 20
VDD5 UV hysteresis VVDD5_UV_HYS 10 50 mV VVDD5_UV 20
VDD5 overvoltage disable threshold VVDD5_OV 5.3 5.5 V Self-checked by HWSC 20
POR release threshold VPOR 4.15 4.45 V Related to VDD5 20
POR hysteresis VPOR_HYS 0.15 0.25 V 20
VDD5 undervoltage filter time tVDD5_UV1 2 2.6 3.25 ms 20
VDD5 overvoltage filter time tVDD5_OV 2 2.6 3.25 ms 20
VDD5 under voltage filter time for NDIS activation tVDD5_UV2 415 500 625 ms 20
POR RESET delay time tPOR_D 10 50 µs POR delay at startup of VDD5 20
VPS operating mode current IVPS_OPM 3 50 mA 21
VPS low battery detection threshold VVPS_UV 3.5 3.8 V 21
Filter time for VPS low battery detection tLBD_FIL 0.5 5 µs 21
VVPS accuracy VPS_ACC -400 400 mV 3.5 V < VVPS < 12 V 21
VVPS accuracy VPS_ACC -3.3 3.3 % 12 V < VVPS < 48 V 21
VPS ADC input range VPS_ADC_in 0 48 V VVPS 21
Charge pump frequency fCP 184 200 216 kHz Dependent on tSYS 22
Charge pump tank capacitor CTANK 420 470 520 nF Connected to VPS IVGBHI = 15 mA 22
Charge pump flying capacitors CFLY 198 220 242 nF Connected between CH1-CH2, CH3-CH4; IVGBHI = 15 mA 22
Under voltage hysteresis VhCP_UV 250 mV Referenced to VVPS 22
Under voltage filter time tCP_UV 10 30 µs 22
Charge pump max voltage VVGBHI_MAX 80 V Referenced to GND 22
Startup time tCPstartup 2 ms 22
Internal absorption when VGNSPx = ON IBIAS_ON 530 µA Internal absorption in when VGNSPx = ON Design info. Not tested in ATE 22
SDO rise and fall time tsdo_trans 5 35 ns CLOAD = 20 to 150 pF 23
Propagation delay SCLK to data at SDO active tpcld 50 ns CLOAD = 150 pF 23
NCS LOW to output SDO active tcsdv 90 ns CLOAD = 150 pF 23
Input capacitance at SDI; SDO; SCLK; NCS CIN_SPI 10 pF 23
Low output level VSDOL 0.4 V ISDO = 3.2 mA 23
Tri state leakage current ISDO_Leak -5 5 µA NCS = HIGH; 0 < VSDO < VIO, 0.3 V 23
Maximum possible peak reverse current at SDO HS before protection Turn Off IOVpeak_SDO_HS 90 250 mA VSDO = 36 V; VIO = 3 V; limited by RDSON only; HS channel On 23
Overvoltage detection analog filter time tOV_SDO_fil 100 700 ns 23
Overvoltage detection HS turn OFF/ON time at SDO tOFF_PROT_OV 0.5 5 µs Includes analog filter time and comparator reaction time until 50% IOVpeak_SDO_HS 23
Gate charge current NMOS ICh0Gx -100 -40 mA GCC[1:0] = [0, 0] 27
Gate charge current NMOS and PMOS ICh1Gx -32.4 -19.6 mA GCC[1:0] = [0, 1] 27
Gate charge current NMOS and PMOS ICh2Gx -8.6 -4 mA GCC[1:0] = [1, 0] 27

CAD (KiCad official)

  • Symbol: L9945TR
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: l9945tr-etched.step / l9945tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l9945tr.step / l9945tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (151 pp, sha256 9d46fef15bb11d30, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF