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L9908TR

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STMicroelectronics Brushless DC (BLDC) Motor Driver, TQFP-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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L9908TR

STMicroelectronics · Brushless DC (BLDC) Motor Driver · TQFP-48-EP(7x7)

L9908TR from STMicroelectronics, in a TQFP-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NCS input SPI Chip Select input, active LOW.
2 SCLK input SPI Serial Clock input, up to 10 MHz per the 32-bit SPI interface.
3 SDI input SPI Serial Data input.
4 SDO output SPI Serial Data output.
5 VIO power_in Power supply for digital outputs, specified at 2.5 V to 5.5 V (VIO_MOR).
6 CSO3/PVM output Current monitor 3 analog output, also used as phase voltage feedback output.
7 CSO2 output Current monitor 2 analog output.
8 CSO1 output Current monitor 1 analog output.
9 VDD power_in Power supply input for internal circuitry and the current monitor analog outputs (CSOn); VDD is the 5 V input from which the 3.3 V internal supply is generated.
10 SGND power_in Signal ground for analog, digital and reference circuits; all analog and digital voltages are referenced to SGND.
11 EN_BR input Bridge Enable input, active HIGH; input low level 0.8 V max, input high level 2 V to 65 V, internal pull-down.
12 NDIS input Safe switch-off activation input, active LOW; input low level 0.8 V max, input high level 2 V to 65 V, internal pull-down.
13 IS3- input Current monitor 3 negative differential input; withstands -14 V to 6 V.
14 IS3+ input Current monitor 3 positive differential input; withstands -14 V to 6 V.
15 IS2- input Current monitor 2 negative differential input; withstands -14 V to 6 V.
16 IS2+ input Current monitor 2 positive differential input; withstands -14 V to 6 V.
17 IS1- input Current monitor 1 negative differential input; withstands -14 V to 6 V.
18 IS1+ input Current monitor 1 positive differential input; withstands -14 V to 6 V.
19 SLS_3 bidirectional Source connection of the low-side FET, phase 3; withstands -14 V to 95 V on motor connection pins.
20 GLS_3 bidirectional Gate connection of the low-side FET, phase 3, driven by the integrated pre-driver.
21 SLS_2 bidirectional Source connection of the low-side FET, phase 2; withstands -14 V to 95 V on motor connection pins.
22 GLS_2 bidirectional Gate connection of the low-side FET, phase 2, driven by the integrated pre-driver.
23 SLS_1 bidirectional Source connection of the low-side FET, phase 1; withstands -14 V to 95 V on motor connection pins.
24 GLS_1 bidirectional Gate connection of the low-side FET, phase 1, driven by the integrated pre-driver.
25 CBS_3 bidirectional Bootstrap capacitor connection of the high-side driver, phase 3.
26 GHS_3 bidirectional Gate connection of the high-side FET, phase 3, driven by the integrated pre-driver.
27 SHS_3 bidirectional Source connection of the high-side FET, phase 3; withstands -14 V to 95 V on motor connection pins.
28 CBS_2 bidirectional Bootstrap capacitor connection of the high-side driver, phase 2.
29 GHS_2 bidirectional Gate connection of the high-side FET, phase 2, driven by the integrated pre-driver.
30 SHS_2 bidirectional Source connection of the high-side FET, phase 2; withstands -14 V to 95 V on motor connection pins.
31 CBS_1 bidirectional Bootstrap capacitor connection of the high-side driver, phase 1.
32 GHS_1 bidirectional Gate connection of the high-side FET, phase 1, driven by the integrated pre-driver.
33 SHS_1 bidirectional Source connection of the high-side FET, phase 1; withstands -14 V to 95 V on motor connection pins.
34 VDH power_in Drain connection of the high-side FETs and motor supply input; motor supply range 4.5 V to 75 V.
35 CP2P bidirectional Charge pump 2 positive terminal of the fly capacitor.
36 CP2M bidirectional Charge pump 2 negative terminal of the fly capacitor.
37 VBP power_in Pre-regulation stage power supply for the gate driver supply.
38 CP1M bidirectional Charge pump 1 negative terminal of the fly capacitor.
39 PGND power_in Power ground for charge pump 1 and charge pump 2.
40 CP1P bidirectional Charge pump 1 positive terminal of the fly capacitor.
41 VPRE bidirectional Pre-regulated voltage used for high-side and low-side FET Vgs driving.
42 INH3 input PWM command for high-side FET, phase 3 (active HIGH).
43 INH2 input PWM command for high-side FET, phase 2 (active HIGH).
44 INH1 input PWM command for high-side FET, phase 1 (active HIGH).
45 INL3 input PWM command for low-side FET, phase 3 (active HIGH).
46 INL2 input PWM command for low-side FET, phase 2 (active HIGH).
47 INL1 input PWM command for low-side FET, phase 1 (active HIGH).
48 FS_FLAG output Fault status flag output, active LOW.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package TQFP-48-EP(7x7)
Category Motor Driver ICs
Pins 49

CAD (KiCad official)

  • Symbol: L9908TR
  • Footprint: Package_QFP:TQFP-48-1EP_7x7mm_P0.5mm_EP5x5mm
  • 3D model: TQFP-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: l9908tr-etched.step / l9908tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l9908tr.step / l9908tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (153 pp, sha256 0427a2705aa0fbf9, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF