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Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	1d ago
viewers	l9780tr: viewers · Ray	1d ago
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l9780tr-etched.step	l9780tr: factory component page (tier=lcsc) · Ray	1d ago
l9780tr-hero.glb	l9780tr: hero GLB from the etched model (keeps the MPN mark) · Ray	7h ago
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README.md	Initial commit: component/l9780tr · Ray	1d ago

L9780TR

STMicroelectronics · Power Management - Specialized · LQFP-48(7x7)

L9780TR from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TG1	passive	Switching TAG resistor pin for channel 1, connected internally to OUT1 through a TG switch of about 4 Ω.
2	SNS	input	VCCS sense pin with a specified SNS common mode range of -2 V to 2.4 V and a short-to-ground threshold of 175 to 225 mV for the positive side.
3	TST1	input	Test mode pin 1, rated from -0.3 V to 40 V.
4	INRC	input	Reference cell input, rated from -0.3 V to +40 V, with a short-to-ground threshold of 175 to 225 mV.
5	RCT1	passive	Impedance test pin 1, rated from -0.3 V to +40 V.
6	RCT2	input	Impedance test amplifier input, rated from -0.3 V to +40 V.
7	SR	passive	Sensor return pin, rated from -VCCA to +40 V, with short-to-battery diagnostic on functional ground.
8	PG1	output	Protection FET gate driver for channel 1, with output swing from 0 to 100 mV low and VCCA minus 0.1 V high at ±10 µA.
9	PG2	output	Protection FET gate driver for channel 2, with output swing from 0 to 100 mV low and VCCA minus 0.1 V high at ±10 µA.
10	HD	input	Heater FET drain, rated from -0.3 V to 53 V with a leakage current of up to 150 µA at 53 V.
11	TST2	input	Test mode pin 2, rated from -0.3 V to 40 V.
12	HG	output	Heater FET gate driver output, swinging from 0 to 100 mV low to VCCA minus 0.2 V high at ±10 µA.
13	SY	input	Synchronous mode pin, rated from -0.3 V to VCCI + 0.3 V.
14	PW	input	Heater PWM input pin, rated from -0.3 V to VCCI + 0.3 V.
15	SO	output	Serial data output of the SPI, rated from -0.3 V to VCCI + 0.3 V.
16	CLK	input	SPI clock input, rated from -0.3 V to VCCI + 0.3 V.
17	SI	input	Serial data input of the SPI, rated from -0.3 V to VCCI + 0.3 V.
18	CSN	input	SPI chip select input, rated from -0.3 V to VCCI + 0.3 V.
19	VCCI	power_in	Digital transfer level supply, rated 3.14 V to 5.1 V.
20	GNDD	power_in	Digital ground.
21	VCCD	power_in	Digital supply, rated 4.9 V to 5.1 V.
22	n.c.	unconnected	Not connected pin.
23	n.c.	unconnected	Not connected pin.
24	n.c.	unconnected	Not connected pin.
25	C1B	passive	Compensation network pin 1, side B, rated from -0.3 V to VCCA + 0.3 V.
26	C2B	passive	Compensation network pin 2, side B, rated from -0.3 V to VCCA + 0.3 V.
27	C3	passive	Compensation network common pin, rated from -0.3 V to VCCA + 0.3 V.
28	C2A	passive	Compensation network pin 2, side A, rated from -0.3 V to VCCA + 0.3 V.
29	C1A	passive	Compensation network pin 1, side A, rated from -0.3 V to VCCA + 0.3 V.
30	FV	passive	VCCS filtered control voltage pin, rated from -0.3 V to VCCA + 0.3 V.
31	FVOUT	output	Analog output of the FVOUT amplifier, rated from -0.3 V to VCCA + 0.3 V.
32	BG	passive	Bandgap voltage pin, rated from -0.3 V to VCCA + 0.3 V.
33	CL2	passive	VCCS voltage clamp channel 2, rated from -0.3 V to VCCA + 0.3 V.
34	CL1	passive	VCCS voltage clamp channel 1, rated from -0.3 V to VCCA + 0.3 V.
35	n.c.	unconnected	Not connected pin.
36	n.c.	unconnected	Not connected pin.
37	VCCCP	power_in	Charge pump supply, rated 4.9 V to 5.1 V.
38	FLCP1	passive	Charge pump floating pin 1, rated from -0.3 V to VCCCP + 0.3 V.
39	FLCP2	passive	Charge pump floating pin 2, rated from CP - 0.3 V to +0.3 V.
40	GNDCP	power_in	Charge pump analog ground.
41	CP	power_out	-5 V charge pump output, rated from -6.5 V to +0.3 V.
42	VESD	passive	ESD reference voltage, rated at 40 V in the maximum ratings and +53 V absolute maximum.
43	GNDA	power_in	Analog ground.
44	VCCA	power_in	Analog supply, rated 4.9 V to 5.1 V.
45	n.c.	unconnected	Not connected pin.
46	TG2	passive	Switching TAG resistor pin for channel 2, connected internally to OUT2 through a TG switch of about 4 Ω.
47	OUT2	output	Pump cell output pin for channel 2, driving the VCCS with a maximum RTOT drop of 1.8 V against SNS.
48	OUT1	output	Pump cell output pin for channel 1, driving the VCCS with a maximum RTOT drop of 1.8 V against SNS.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	LQFP-48(7x7)
Category	Power Management (PMIC)
Pins	48

CAD (KiCad official)

Symbol: L9780TR
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: l9780tr-etched.step / l9780tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l9780tr.step / l9780tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (56 pp, sha256 bf560dfa5f013e54, retrieved 2026-10-07, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF