# L9616

**ST(意法半导体)** · CAN ICs · SOIC-8

L9616 from ST(意法半导体), in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TXO | input | Transmitter input; high level input at least 0.7 VS, low level at most 0.3 VS, DC voltage range GND-0.3 V to VS+0.3 V. |
| 2 | GND | power_in | Ground; all voltages except bus voltage are defined with respect to this pin. |
| 3 | VS | power_in | Supply voltage, 4.5 to 5.5 V operating, absolute maximum -0.3 to 7 V. |
| 4 | RXO | output | Receive output; output current limited to -0.3 to 1 mA, low level max 0.5 V at 1 mA. |
| 5 | RX1 | output | Reference voltage output of 0.5 VS typical (0.45 to 0.55 VS) with 2 to 9 kOhm output resistance. |
| 6 | C_L | bidirectional | Low side CAN bus output/input, short circuit protected for -5 V to 36 V with overvoltage threshold of 7 to 10 V. |
| 7 | C_H | bidirectional | High side CAN bus output/input, short circuit protected for -5 V to 36 V. |
| 8 | ASC | input | Adjustable slope control; tie to GND for high speed up to 1 Mbaud, tie to VS for low speed up to 250 kbaud with reduced slew rate. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | ST(意法半导体) |
| Package | SOIC-8 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VS | 4.5 | 5 | 5.5 | V |  | 7 |
| Supply current dominant | IS |  |  | 80 | mA | Dominant | 7 |
| Supply current recessive | IS |  |  | 20 | mA | Recessive | 7 |
| TXO input capacitance | CTXO |  | 25 |  | pF | 0 V < VTXO < VS | 7 |
| TXO high level input voltage | VTXO | 0.7 |  |  | V | min 0.7 VS, max VS as printed (V in VS multiples) | 7 |
| TXO low level input voltage | VTXO |  | 0 | 0.3 | V | max 0.3 VS as printed | 7 |
| TXO high level input current | ITXO | -2 | 0 | 2 | μA | VTXO = VS | 7 |
| TXO low level input current | ITXO | -275 | 0 | -25 | μA | VTXO = GND | 7 |
| ASC input capacitance | CASC |  | 25 |  | pF | 0 V < VASC < VS | 7 |
| ASC input voltage for high speed | VASC |  | 0 | 0.1 | V | max 0.1 VS as printed | 8 |
| ASC input voltage for low speed | VASC | 0.9 |  |  | V | min 0.9 VS, max VS as printed | 8 |
| ASC input current | IASC | 25 |  | 275 | μA | VASC = VS | 8 |
| ASC input current | IASC | -2 | 0 | 2 | μA | VASC = 0 V | 8 |
| Bus voltage recessive | VC_H, VC_L | 0.4 | 0.5 | 0.6 | V | Recessive; values are multiples of VS (0.4 VS/0.5 VS/0.6 VS) | 8 |
| Leakage current recessive | IC_H, IC_L | -0.7 |  | 0.7 | mA | VC_L = VC_H = -2 to 7 V | 8 |
| Leakage current recessive | IC_H, IC_L | -0.3 |  | 0.3 | mA | VC_L = VC_H = 1 to 4 V | 8 |
| Input resistance | RIN(C_H, C_L) | 5 |  | 50 | kΩ | Recessive | 8 |
| Differential input resistance | RDiff(C_H, C_L) | 10 |  | 100 | kΩ | Recessive | 8 |
| Differential output voltage dominant | VDiff | 1.5 |  | 3 | V | Dominant, RA | 8 |
| Differential output voltage recessive | VDiff | -500 | 0 | 50 | mV | Recessive | 8 |
| Short circuit detection time | td | 1 | 5 | 10 | s | C_H to C_L; C_H to B RCS < 1 Ω | 8 |
| Supply current in case of short circuit | IA |  | 150 |  | mA | C_H to C_L, C_H to B (time = td) | 8 |
| Overvoltage protection threshold on C_L | VC_Lmax | 7 | 8 | 10 | V |  | 8 |
| RXO high level output voltage | VRXO | 0.9 |  |  | V | VDiff < 0.5 V; IRXO = 0.3 mA; VC_H = -2 to 7 V; VC_L = -2 to 7 V; min 0.9 VS, max VS as printed | 8 |
| RXO low level output voltage |  |  |  | 0.5 | V | VDiff > 0.9 V; IRXO = 1 mA; VC_H = -2 to 7 V; VC_L = -2 to 7 V | 8 |
| Input signal threshold | VDiff | 500 | 700 | 900 | mV | VC_H = -2 to 7 V; VC_L = -2 to 7 V | 8 |
| Input common mode voltage range | VCOM | -2 |  | 7 | V |  | 8 |
| Differential input hysteresis | VHYS |  | 150 |  | mV |  | 8 |
| Reference voltage | VRX1 | 0.45 | 0.5 | 0.55 | V | IRX1 = 0; values are multiples of VS | 8 |
| Output resistance RX1 | RRX1 | 2 |  | 9 | kΩ |  | 8 |
| Signal delay TXO to C_H, C_L | tOT |  |  | 50 | ns |  | 9 |
| Differential output slew rate | SR | 20 |  | 50 | V/μs | VASC = 0 V | 9 |
| Differential output slew rate | SR | 5 |  | 20 | V/μs | VASC = VS | 9 |
| Signal delay C_H, C_L to RXO | tOR |  |  | 150 | ns | VASC = 0 V | 9 |
| Signal delay TXO to RXO | tOTR |  |  | 300 | ns | VASC = 0V | 9 |
| Supply voltage | VS | -0.3 |  | 7 | V |  | 7 |
| Bus voltage at C_H, C_L | VC_H, VC_L | -5 |  | 36 | V | VS = 0 to 5.5 V | 7 |
| Off state leakage current at C_H, C_L | IC_H, IC_L | -3 |  | 5 | mA | VS = 0 to 5.5 V, VC_H = -5 to 36 V, VC_L = -5 to 36 V | 7 |
| DC voltage at TXO, ASC | VDC | -0.3 |  | 0.3 | V | VS = 0 to 5.5 V; printed GND -0.3 to VS +0.3 | 7 |
| Output current at RXO | IRXO | -0.3 |  | 1 | mA | VS = 0 to 5.5 V | 7 |
| Storage and junction temperature range | Tstg, TJ | -40 |  | 150 | °C |  | 7 |
| Operating temperature range | Top | -40 |  | 125 | °C |  | 7 |

## CAD (KiCad official)

- Symbol: `L9616`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `l9616-etched.step` / `l9616-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `l9616.step` / `l9616.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [ST(意法半导体) datasheet](docs/l9616-datasheet.pdf) (17 pp, sha256 `53f2c4c3d2a9d3fe`, retrieved 2026-10-27, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/l9616-datasheet.pdf)