# L9012PLT1G

**LRC** · Bipolar (BJT) · SOT-23

L9012PLT1G from LRC, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BASE | input | Base terminal of the PNP transistor, which controls the collector-emitter current. |
| 2 | EMITTER | passive | Emitter terminal of the PNP transistor; the datasheet rates the device at VCEO -20 V, VCBO -40 V, VEBO -5 V and continuous collector current -500 mA. |
| 3 | COLLECTOR | passive | Collector terminal of the PNP transistor, rated at VCBO -40 V and continuous collector current -500 mA. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SOT-23 |
| Category | Transistors/Thyristors |
| Pins | 3 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Collector-Emitter Breakdown Voltage | V(BR)CEO | -20 |  |  | V | IC=-1.0mA | 1 |
| Emitter-Base Breakdown Voltage | V(BR)EBO | -5 |  |  | V | IE=-100 µA | 1 |
| Collector-Base Breakdown Voltage | V(BR)CBO | -40 |  |  | V | IC=-100 µA | 1 |
| Collector Cutoff Current | ICBO |  |  | -150 | nA | VCB=-35V | 1 |
| Emitter Cutoff Current | IEBO |  |  | -150 | nA | VBE=-4V | 1 |
| DC Current Gain (grade P) | hFE | 100 |  | 200 |  | IC=-50mA, VCE=-1V | 2 |
| Collector-Emitter Saturation Voltage | VCE(S) |  |  | -0.6 | V | IC=-500mA, IB=-50mA | 2 |
| Collector-Emitter Voltage | VCEO |  |  | -20 | V |  | 1 |
| Collector-Base Voltage | VCBO |  |  | -40 | V |  | 1 |
| Emitter-Base Voltage | VEBO |  |  | -5 | V |  | 1 |
| Collector current-continuous | IC |  |  | -500 | mAdc |  | 1 |
| Total Device Dissipation, FR-5 Board | PD |  |  | 225 | mW | TA=25°C, FR-5 board (1.0 x 0.75 x 0.062 in.) | 1 |
| Total Device Dissipation, Alumina Substrate | PD |  |  | 300 | mW | TA=25°C, alumina substrate (0.4 x 0.3 x 0.024 in.) | 1 |
| Thermal Resistance, Junction to Ambient, FR-5 Board | RθJA |  |  | 556 | °C/W | FR-5 board (1.0 x 0.75 x 0.062 in.) | 1 |
| Thermal Resistance, Junction to Ambient, Alumina Substrate | RθJA |  |  | 417 | °C/W | Alumina substrate (0.4 x 0.3 x 0.024 in.) | 1 |
| Junction and Storage Temperature | Tj, Tstg | -55 |  | 150 | °C |  | 1 |

## CAD (KiCad official)

- Symbol: `L9012PLT1G`
- Footprint: `Package_TO_SOT_SMD:SOT-23`
- 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files: `l9012plt1g-etched.step` / `l9012plt1g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `l9012plt1g.step` / `l9012plt1g.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [LRC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588945181828141056) (2 pp, sha256 `4b70db4795a4f985`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/l9012plt1g-datasheet.pdf)