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Generated by kicad-footprint-generator · KiCad file format 20260206

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L8550HPLT1G

LRC · MOSFETs · SOT-23

L8550HPLT1G from LRC, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	BASE	input	Base terminal of the PNP transistor (L8550HPLT1G, SOT-23); the datasheet gives no separate pin-level limit, so the device ratings apply, including VCEO -25 V, VCBO -40 V and IC -1500 mAdc maximum.
2	EMITTER	passive	Emitter terminal of the PNP transistor; the emitter-base breakdown voltage is V(BR)EBO -5 V minimum at IE = -100 µA, and VEBO is -5 V in the absolute-maximum table as printed.
3	COLLECTOR	passive	Collector terminal of the PNP transistor, rated for a collector current of -1500 mAdc maximum with VCEO -25 V and VCBO -40 V, junction and storage temperature -55 to +150 °C.

Key specifications

Parameter	Value
Manufacturer	LRC
Package	SOT-23
Category	Transistors/Thyristors
Pins	3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Max	Unit	Conditions	Page
Collector-Emitter Breakdown Voltage	V(BR)CEO	-25		V	IC=-1.0mA	2
Emitter-Base Breakdown Voltage	V(BR)EBO	-5		V	IE=-100µΑ	2
Collector-Base Breakdown Voltage	V(BR)CBO	-40		V	IC=-100µΑ	2
Collector Cutoff Current	ICBO		-150	nA	VCB=-35V	2
Emitter Cutoff Current	IEBO		-150	nA	VEB=-4V	2
DC Current Gain (P grade)	hFE	100	200		IC=-100mA,VCE=-1V	2
Collector-Emitter Saturation Voltage	VCE(S)		-0.5	V	IC=-800mA,IB=-80mA	2
Collector-Emitter Voltage	VCEO		-25	V		1
Collector-Base Voltage	VCBO		-40	V		1
Collector Current			-1500	mAdc		1
Total Device Dissipation, FR-5 Board	PD		225	mW	FR-5 Board, TA=25°C	1
Derate above 25°C, FR-5 Board	PD		1.8	mW/°C	Derate above 25°C	1
Thermal Resistance, Junction to Ambient, FR-5 Board	RθJA		556	°C/W	FR-5 Board	1
Total Device Dissipation, Alumina Substrate	PD		300	mW	Alumina Substrate, TA=25°C	1
Derate above 25°C, Alumina Substrate	PD		2.4	mW/°C	Derate above 25°C	1
Thermal Resistance, Junction to Ambient, Alumina Substrate	RθJA		417	°C/W	Alumina Substrate	1
Junction and Storage Temperature	Tj,Tstg	-55	150	°C		1

CAD (KiCad official)

Symbol: L8550HPLT1G
Footprint: Package_TO_SOT_SMD:SOT-23
3D model: SOT-23 (KiCad packages3D, STEP)
3D model files: l8550hplt1g-etched.step / l8550hplt1g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l8550hplt1g.step / l8550hplt1g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: LRC datasheet (3 pp, sha256 7f872a6303252e9a, retrieved 2026-10-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF