L7987 from STMicroelectronics, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VBIAS	input	VBIAS is an auxiliary input that supplies part of the analog circuitry to improve light-load efficiency, typically connected to the regulated output or to an external rail higher than 3 V, and must be connected to signal GND if unused.
2	VIN	power_in	VIN is the DC input voltage pin, with an operating input voltage range of 4.5 V to 61 V.
3	VIN	power_in	VIN is the DC input voltage pin, with an operating input voltage range of 4.5 V to 61 V.
4	VCC	power_in	VCC is the filtered DC input voltage for the internal circuitry and must be bypassed to signal GND by a 1 µF ceramic capacitor.
5	EN	input	EN is an active-high enable pin with device OFF level up to 0.30 V and device ON level from 0.35 V, and should be connected to VCC if not used.
6	SS	passive	An internal current generator (5 µA typ.) charges the external capacitor to implement the soft-start.
7	SYNCH	bidirectional	SYNCH is the master/slave synchronization pin, allowing multiple devices to be synchronized to prevent beating noise.
8	COMP	output	COMP is the output of the error amplifier, where the designed compensation network is connected.
9	FB	input	FB is the inverting input of the error amplifier, with a voltage feedback reference of 0.800 V typ.
10	FSW	input	A pull-down resistor from FSW to GND selects the switching frequency, which is adjustable from 250 kHz to 1.5 MHz.
11	ILIM	input	A pull-down resistor from ILIM to GND selects the peak current limitation.
12	PGOOD	output	The PGOOD open collector output is driven low when the output voltage sensed on FB is out of regulation.
13	LX	output	LX is the switching node of the regulator.
14	LX	output	LX is the switching node of the regulator.
15	BOOT	passive	An external capacitor (100 nF typ.) connected between BOOT and LX supplies the gate charge for the internal n-DMOS, recovered by an internal regulator during the off-time.
16	GND	power_in	GND is the signal ground pin of the device.
17	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	HTSSOP-16-EP
Category	Power Management (PMIC)
Pins	17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input voltage	VIN	-0.3		61	V		7
VCC input voltage	VCC	-0.3		61	V		7
BOOT to GND voltage	VBOOT - GND	-0.3		65	V		7
BOOT to LX voltage	VBOOT - VLX	-0.3		4	V		7
VBIAS voltage	VBIAS	-0.3			V	max printed as VCC	7
EN voltage	EN	-0.3			V	max printed as VCC	7
PGOOD voltage	PGOOD	-0.3			V	max printed as VCC	7
LX voltage	LX	-0.3			V	max printed as VIN + 0.3	7
SYNCH voltage	SYNCH	-0.3		5.5	V		7
SS voltage	SS	-0.3		3.6	V		7
FSW voltage	FSW	-0.3		3.6	V		7
COMP voltage	COMP	-0.3		3.6	V		7
ILIM voltage	ILIM	-0.3		3.6	V		7
FB voltage	FB	-0.3		3.6	V		7
Operating temperature range	TJ	-40		150	°C		7
Storage temperature range	TSTG	-65		150	°C		7
Lead temperature (soldering 10 sec.)	TLEAD			260	°C	soldering 10 sec.	7
High-side RMS current	IHS			3	A		7
Operating input voltage range	VIN	4.5		61	V		8
High side RDSON	RDSON		0.2	0.32	Ω	ISW = 0.5 A	8
High side RDSON (1)	RDSON		0.2	0.42	Ω	ISW = 0.5 A (1)	8
Switching frequency	fSW	233	250	267	kHz	FSW floating	8
Switching frequency (1)	fSW	225	250	275	kHz	FSW floating (1)	8
Selected switching frequency	fSW	1350	1500	1650	kHz	RSW = 10 k	8
Peak current limit	IPK	3.4	4	4.6	A	ILIM floating; VFB = 0.6 V (2)	8
Selected peak current limit	IPK	0.68	0.85	1.01	A	RILIM = 100 k VFB = 0.6 V (2)	8
VCC UVLO rising threshold	VCCH	3.85	4.1	4.3	V	(1)	8
VCC UVLO hysteresis	VCCHYST	160	250	340	mV	(1)	8
VBIAS threshold	SWO	2.84	2.9	2.96	V	Switch internal supply from VCC to VBIAS. VBIAS ramping up from 0 V. (1)	8
VCC - VBIAS threshold	VCC - VBIAS	3.35	4.05	4.9	V	Switch internal supply from VCC to VBIAS. VIN = VCC = 24 V, VBIAS falling from 24 V to GND. (1)	8
Quiescent current from VIN and VCC	IQUIESC		2.5	3.4	mA	LX floating, VFB = 1 V, VBIAS = GND, FSW floating	8
Quiescent current from VIN and VCC	IQOPVIN		1	1.4	mA	LX floating, VFB = 1 V, VBIAS = 3.3 V, FSW floating	8
Quiescent current from VBIAS	IQOPVBIAS		1.6	2.4	mA		8
Shutdown current from VIN	ISHTDWN		11	16	µA	VEN = GND	8
Device OFF level	VEN	0.06		0.3	V		9
Device ON level	VEN	0.35		0.9	V		9
CSS charging current	ISS CH	4.3	5	5.7	µA	VSS = GND	9
Voltage feedback	VFB	0.792	0.8	0.808	V		9
Voltage feedback (1)	VFB	0.788	0.8	0.812	V	(1)	9
VCOMP high level	VCOMPH	3.2	3.35	3.5	V	VFB = GND; VSS = 3.2 V	9
VCOMP low level	VCOMPL		0.1		V	VFB =1 V; VSS = 3.2 V	9
FB biasing current	IFB		5	50	nA	VFB =3.6 V	9
Output stage sinking capability	IOSINK		5		mA	Unity gain buffer configuration (FB connected to COMP). COMP voltage variation due to IOSINK injection lower than ± 0.1 · VFB	9
Synchronization frequency	fSYN MIN	280			kHz	FSW floating	9
Master output pulse width	VSYNOW	155	225	275	ns	ILOAD = 0 A; pin SYNCH floating	9
SYNCH slave high level input threshold	VSYNIH	2			V		9
SYNCH slave low level input threshold	VSYNIL			1	V		9
Slave SYNCH pull-down current	ISYN	550	750	950	µA	VSYNCH = 5 V	9
PGOOD rising threshold	VPGDTH	0.67	0.7	0.73	V	VFB rising	9
PGOOD hysteresis	VPGDHYST		30		mV	VFB falling (3)	9
Thermal shutdown temperature	TSHDWN		170		°C	(3)	10
Thermal shutdown hysteresis	THYS		15		°C	(3)	10
Thermal resistance junction-ambient	RthJA		40		°C/W	device soldered on the STMicroelectronics demonstration board	7
Minimum on time	TONMIN	120	150		ns		8
Maximum on time	TONMAX		12		µs		8
Pulse skipping peak current	ISKIP		0.5		A	(2)	8
Feedback foldback level	VFOLD		400		mV	(3)	8
Minimum off time	TOFFMIN		360		ns	(3)	8
VBIAS threshold hysteresis	SWO		80		mV	(3)	8
VCC - VBIAS threshold hysteresis	VCC - VBIAS		750		mV	(3)	8

CAD (KiCad official)

Symbol: L7987
Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
3D model: HTSSOP-16-EP (KiCad packages3D, STEP)
3D model files: l7987-etched.step / l7987-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l7987.step / l7987.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (37 pp, sha256 481abe81339105aa, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

L7987

Verified L7987

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3D Model

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