# L7986TATR

**STMicroelectronics** · DC-DC Converters · SOIC-8

L7986TATR from STMicroelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | output | Regulator output; the absolute maximum DC output voltage is -0.3 V to VCC. |
| 2 | SYNCH | bidirectional | Master/slave synchronization pin that carries a half-period phase-shifted signal when floating and synchronizes to an external higher-frequency signal with zero phase shift; the absolute maximum rating for this analog pin is -0.3 V to 4 V. |
| 3 | EN | input | Active-high enable that turns the device ON above 1.2 V and OFF below 0.3 V, with an absolute maximum range of -0.3 V to VCC. |
| 4 | COMP | output | Error amplifier output used for loop frequency compensation; the datasheet gives high-level output of 3 V (VFB < 0.6 V) and low-level output of 0.1 V (VFB > 0.6 V). |
| 5 | FB | input | Feedback input that regulates the output at 0.6 V when VOUT is connected directly, with an external resistor divider needed for higher voltages and an absolute maximum range of -0.3 V to 1.5 V. |
| 6 | FSW | passive | Switching frequency pin where an external resistor to ground raises the frequency, and a floating pin gives the free-running 250 kHz; the absolute maximum rating for this analog pin is -0.3 V to 4 V. |
| 7 | GND | power_in | Ground reference pin for the device. |
| 8 | VCC | power_in | Unregulated DC input voltage with an operating range of 4.5 V to 38 V and an absolute maximum of 45 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage | Vcc |  |  | 45 | V |  | 5 |
| Output DC voltage | VOUT | -0.3 |  |  | V |  | 5 |
| Analog pin voltage (FSW, COMP, SYNCH) | FSW, COMP, SYNCH | -0.3 |  | 4 | V |  | 5 |
| Enable pin voltage | EN | -0.3 |  |  | V |  | 5 |
| Feedback voltage | FB | -0.3 |  | 1.5 | V |  | 5 |
| Power dissipation HSOP8 | PTOT |  |  | 2 | W | TA < 60 °C | 5 |
| Junction temperature range | TJ | -40 |  | 150 | °C |  | 5 |
| Storage temperature range | Tstg | -55 |  | 150 | °C |  | 5 |
| Maximum thermal resistance junction ambient HSOP8 | RthJA |  |  | 40 | °C/W | Package mounted on demonstration board | 5 |
| Operating input voltage range | VCC | 4.5 |  | 38 | V |  | 6 |
| Turn-on VCC threshold | VCCON |  | 4.5 |  | V |  | 6 |
| VCC UVLO hysteresis | VCCHYS | 0.1 |  | 0.4 | V |  | 6 |
| MOSFET on resistance | RDSON | 200 |  | 400 | mΩ |  | 6 |
| Maximum limiting current | ILIM | 3.7 | 4.2 | 4.7 | A | TJ = 25 °C | 6 |
| Maximum limiting current | ILIM | 3.5 |  | 4.7 | A |  | 6 |
| Switching frequency | FSW | 210 | 250 | 275 | KHz |  | 6 |
| FSW pin voltage | VFSW |  | 1.254 |  | V |  | 6 |
| Duty cycle | D | 0 |  | 100 | % |  | 6 |
| Adjustable switching frequency | FADJ |  |  | 1000 | KHz | RFSW = 33 k | 6 |
| Feedback voltage | VFB | 0.582 | 0.6 | 0.618 | V | 4.5 V < VCC < 38 V | 6 |
| Quiescent current | IQ |  |  | 2.4 | mA | Duty cycle = 0, VFB = 0.8 V | 6 |
| Total standby quiescent current | IQST-BY | 20 |  | 30 | µA |  | 6 |
| EN threshold voltage, device OFF level | VEN |  |  | 0.3 | V | Device OFF level | 6 |
| EN threshold voltage, device ON level | VEN | 1.2 |  |  | V | Device ON level | 6 |
| EN current | IEN | 7.5 |  | 10 | µA | EN = VCC | 6 |
| Soft-start duration | TSS | 7.4 | 8.2 | 9.7 | ms | FSW pin floating | 6 |
| High level output voltage | VCH | 3 |  |  | V | VFB < 0.6 V | 6 |
| Low level output voltage | VCL |  |  | 0.1 | V | VFB > 0.6 V | 6 |
| Source current COMP pin | IO SOURCE | 19 |  |  | mA | VFB = 0.5 V, VCOMP = 1 V | 6 |
| Sink current COMP pin | IO SINK | 30 |  |  | mA | VFB = 0.7 V, VCOMP = 1 V | 7 |
| Open-loop voltage gain | GV | 100 |  |  | dB |  | 7 |
| Synchronization high input voltage | VS_IN,HI | 2 |  | 3.3 | V |  | 7 |
| Synchronization low input voltage | VS_IN,LO |  |  | 1 | V |  | 7 |
| Input pulse width | tS_IN_PW | 100 |  |  | ns | VS_IN,HI = 3 V, VS_IN,LO = 0 V | 7 |
| Input pulse width | tS_IN_PW | 300 |  |  | ns | VS_IN,HI = 2 V, VS_IN,LO = 1 V | 7 |
| Slave sink current | ISYNCH,LO | 0.7 |  | 1 | mA | VSYNCH = 2.9 V | 7 |
| Master output amplitude | VS_OUT,HI | 2 |  |  | V | ISOURCE = 4.5 mA | 7 |
| Output pulse width | tS_OUT_PW |  | 110 |  | ns | SYNCH floating | 7 |
| Thermal shutdown | TSHDN |  | 150 |  | °C |  | 7 |
| Thermal shutdown hysteresis |  |  | 30 |  | °C |  | 7 |

## CAD (KiCad official)

- Symbol: `L7986TATR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `l7986tatr-etched.step` / `l7986tatr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `l7986tatr.step` / `l7986tatr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588924829075951616) (42 pp, sha256 `6fbde02e437f5e16`, retrieved 2026-10-12, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/l7986tatr-datasheet.pdf)