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L78M05CDT-TR

Public Made by Adom

by adom

STMicroelectronics Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, TO-252-2(DPAK). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs l78m05cdt-tr: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain S… · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
l78m05cdt-tr-etched.fit.json l78m05cdt-tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
l78m05cdt-tr-etched.glb l78m05cdt-tr: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain S… · Ray
l78m05cdt-tr-etched.step l78m05cdt-tr: etch along the lead row, tab up; full MPN text (service-occt 1.9.3) (service-occt 1.6.0, from the plain S… · Ray
l78m05cdt-tr-hero.glb Publish 0.2.1 · Ray
l78m05cdt-tr-hero.overlay.json Publish 0.2.1 · Ray
l78m05cdt-tr.glb Publish 0.1.0 · Ray
l78m05cdt-tr.kicad_mod Publish 0.1.0 · Ray
l78m05cdt-tr.kicad_sym Publish 0.1.0 · Ray
l78m05cdt-tr.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
l78m05cdt-tr.step Publish 0.1.0 · Ray
package.json Publish 0.2.1 · Ray
pads.json page.json: fold the "TAB" entry into pin 2. On TO-252-2 the tab is not a separate pad - it is that lead - so nothing wa… · Ray
page.json Publish 0.2.1 · Ray
README.md l78m05cdt-tr: specified limits as data (metadata.characteristics, 19 rows from the datasheet) · Ray

L78M05CDT-TR

STMicroelectronics · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · TO-252-2(DPAK)

L78M05CDT-TR from STMicroelectronics, in a TO-252-2(DPAK). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 INPUT power_in Unregulated positive DC input. Absolute maximum 35 V (for 5-18 V output versions). Bypass to GND with a 0.33 uF ceramic close to the pin for stability.
2 GROUND power_in Common ground reference. Internally connected to the exposed thermal tab of the DPAK package; both must be tied to the system ground plane for return current and heatsinking.
3 OUTPUT power_out Regulated +5 V output, 500 mA rated (higher with adequate heatsinking). Requires a 0.1 uF ceramic to GND close to the pin for transient response and stability.
TAB GROUND power_in Exposed thermal pad on the back of the DPAK, electrically tied to the GROUND pin (pin 2). Must be soldered to a copper pour to remove heat (RthJC = 8 degC/W).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package TO-252-2(DPAK)
Category PMIC
Pins 4

Ordering variants

Same part, different packaging or reel option.

  • L78M05CDT-TR
  • L78M05CDT-TRCV
  • L78M05CDT-TRCP
  • L78M05CDT-TRCH

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output voltage VO 4.8 5 5.2 V 7
Output voltage VO 4.75 5 5.25 V IO = 5 to 350 mA, VI = 7 to 20 V 7
Line regulation ΔVO 100 mV VI = 7 to 25 V, IO = 200 mA 7
Line regulation ΔVO 50 mV VI = 8 to 25 V, IO = 200 mA 7
Load regulation ΔVO 100 mV IO = 5 to 500 mA, TJ = 25 °C 7
Load regulation ΔVO 50 mV IO = 5 to 200 mA, TJ = 25 °C 7
Quiescent current Id 6 mA 7
Quiescent current change ΔId 0.5 mA IO = 5 to 350 mA 7
Quiescent current change ΔId 0.8 mA IO = 200 mA, VI = 8 to 25 V 7
Dropout voltage Vd 2 V 7
DC input voltage VI 35 V for VO = 5 to 18 V 5
Storage temperature range TSTG -65 150 °C 5
Operating junction temperature range TOP 0 150 °C for L78MxxC 5
Output voltage drift ΔVO/ΔT -0.5 mV/°C IO = 5 mA, TJ = 0 to 125 °C 7
Supply voltage rejection SVR 62 dB VI = 8 to 18 V, f = 120 Hz, IO = 300 mA 7
Output noise voltage eN 40 µV B = 10 Hz to 100 kHz 7
Short circuit current Isc 300 mA VI = 35 V 7
Thermal resistance junction-case (DPAK) RthJC 8 °C/W DPAK 5
Thermal resistance junction-ambient (DPAK) RthJA 100 °C/W DPAK 5

CAD (KiCad official)

  • Symbol: L78M05CDT-TR
  • Footprint: Package_TO_SOT_SMD:TO-252-2
  • 3D model: TO-252-2(DPAK) (KiCad packages3D, STEP)
  • 3D model files: l78m05cdt-tr-etched.step / l78m05cdt-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l78m05cdt-tr.step / l78m05cdt-tr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
l78m05cdt-tr.step 119 KB You want the bare part, or you mark your own boards.
l78m05cdt-tr-etched.step 1.7 MB You want the part with L78M05CDT-TR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 452 faces against 83 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (45 pp, sha256 aab13a77a9bc7601, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF