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L78L33ACD13TR

Public Made by Adom

by adom

STMicroelectronics Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs l78l33acd13tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
l78l33acd13tr-etched.fit.json l78l33acd13tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
l78l33acd13tr-etched.glb l78l33acd13tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
l78l33acd13tr-etched.step l78l33acd13tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
l78l33acd13tr.glb Publish 0.1.0 · Ray
l78l33acd13tr.kicad_mod Publish 0.1.0 · Ray
l78l33acd13tr.kicad_sym Publish 0.1.0 · Ray
l78l33acd13tr.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
l78l33acd13tr.step Publish 0.1.0 · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json l78l33acd13tr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md l78l33acd13tr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

L78L33ACD13TR

STMicroelectronics · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8

L78L33ACD13TR from STMicroelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUT power_out Regulated 3.3 V DC output (typ. 3.3 V, min 2.97 V, max 3.63 V over 1-70 mA). Requires a 0.1 uF ceramic output capacitor to ground for stability. Delivers up to 100 mA.
2 GND power_in Ground reference. In the SO-8 package pins 2, 3, 6 and 7 are internally commoned to the die attach flag to improve thermal dissipation; all four should be tied to the ground plane with a copper heat-sink area (approx. 6 cm^2) for the specified thermal resistance.
3 GND power_in Ground / thermal pad connection. Internally commoned to the die attach flag together with pins 2, 6 and 7.
4 NC unconnected No internal connection. Leave floating or tie to ground for lowest parasitic coupling.
5 NC unconnected No internal connection. Leave floating or tie to ground for lowest parasitic coupling.
6 GND power_in Ground / thermal pad connection. Internally commoned to the die attach flag together with pins 2, 3 and 7.
7 GND power_in Ground / thermal pad connection. Internally commoned to the die attach flag together with pins 2, 3 and 6.
8 VIN power_in Unregulated DC input. Absolute maximum 30 V for 3.3 V output variants; recommended operating range 5.3 V to 20 V (dropout typ. 2 V). A 0.33 uF ceramic input capacitor to ground is required close to the pin when the device is far from the bulk filter capacitor.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SOIC-8
Category PMIC
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • L78L33ACD13TRD
  • L78L33ACD13TRD-TR
  • L78L33ACD13TR
  • L78L33ACD13TRZ
  • L78L33ACD13TRAZ
  • L78L33ACD13TRACZ
  • L78L33ACD13TRACUTR

CAD (KiCad official)

  • Symbol: L78L33ACD13TR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: l78l33acd13tr-etched.step / l78l33acd13tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l78l33acd13tr.step / l78l33acd13tr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
l78l33acd13tr.step 122 KB You want the bare part, or you mark your own boards.
l78l33acd13tr-etched.step 2.5 MB You want the part with L78L33ACD13TR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 621 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (45 pp, sha256 43922ae159face7e, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF